Abstract: This disclosure provides systems, methods, and devices for wireless communications that support configurable local oscillator circuitry. In a first aspect, transceiver system includes one or more receive or transmit chains, and a particular chain thereof includes one or more dividers configured to receive a clock signal. The particular chain also includes local oscillator (LO) cross routing circuitry coupled to the one or more dividers and includes a mixer coupled to the LO cross routing circuitry. The particular chain further includes one or more auxiliary mixers coupled to the LO cross routing circuitry, and the LO cross routing circuitry is configured to selectively couple a particular divider of the one or more dividers to the mixer, to at least one auxiliary mixer of the one or more auxiliary mixers, or any combination thereof. Other aspects and features are also claimed and described.

Abstract: Certain aspects of the present disclosure are directed towards a method for delay element calibration. The method generally includes: incrementing a calibration delay control signal provided to a delay element to generate an output clock signal by delaying an input clock signal; comparing, via a phase detector (PD), the input clock signal and the output clock signal to generate a PD output signal; and accumulating, via a first accumulator, the PD output signal to generate a calibration output signal.

Abstract: A two-stage circuit includes a differential-to-single-ended first stage with a differential pair of transistors. The first stage includes a current mirror including a diode-connected transistor having an RC circuit coupled to a drain of the diode-connected transistor. The current mirror is configured to mirror a power supply noise current conducted by the RC circuit through a first stage output terminal to a gate of an output transistor in a second stage of the two-stage circuit.

Abstract: This disclosure describes apparatuses, methods, and techniques for implementing a multimode frequency multiplier. In example implementations, an apparatus for generating a frequency includes a multimode frequency multiplier. The multimode frequency multiplier includes a multiphase generator and a reconfigurable frequency multiplier. The multiphase generator is configured to produce a first signal including multiple phase components and having a first frequency. The reconfigurable frequency multiplier is coupled in series with the multiphase generator. The reconfigurable frequency multiplier is configured to produce a second signal based on the first signal and having a second frequency that is a multiple of the first frequency.

Abstract: This disclosure describes apparatuses, methods, and techniques for implementing a multimode frequency multiplier. In example implementations, an apparatus for generating a frequency includes a multimode frequency multiplier. The multimode frequency multiplier includes a multiphase generator and a reconfigurable frequency multiplier. The multiphase generator is configured to produce a first signal including multiple phase components and having a first frequency. The reconfigurable frequency multiplier is coupled in series with the multiphase generator. The reconfigurable frequency multiplier is configured to produce a second signal based on the first signal and having a second frequency that is a multiple of the first frequency.

Abstract: A frequency divider functionality detection and adjustment circuit includes an auxiliary voltage controlled oscillator (VCO) coupled to a first multiplexer (MUX), a programmable divider coupled to the first MUX, a second MUX coupled to the programmable divider, a counter coupled to the second MUX, and a controller coupled to the counter, the controller configured to adjust a supply voltage provided to the programmable divider based on a measured divide ratio, NMEAS.

Abstract: A hybrid true single-phase clock (H-TSPC) circuit includes a first logic circuit comprising non-ratio (NR) logic, a first mode switching device coupled to an output of the first logic circuit, a second logic circuit comprising ratio (R) logic, the second logic circuit configured to receive an output of the first logic circuit, a second mode switching device coupled to an output of the second logic circuit, a third logic circuit comprising non-ratio (NR) logic, the third logic circuit configured to receive an output of the second logic circuit, and a third mode switching device coupled to an output of the third logic circuit, wherein the first logic circuit, second logic circuit, and third logic circuit are configured in a ring.

Abstract: Aspects of the disclosure relate to a ring oscillator (RO) frequency divider configured to frequency divide an input clock by a programmable divider ratio to generate an output clock. In this regard, the RO frequency divider receives the input clock, enables each of a ring of N cascaded inverter stages substantially one at a time in response to the input clock; and outputs a second clock from an output of one of the ring of N cascaded inverter stages. In one aspect, each stage includes a p-channel metal oxide semiconductor field effect transistor (PMOS FET) coupled in series with an n-channel metal oxide semiconductor field effect transistor (NMOS FET). In another, each stage includes two PMOS FETs and an NMOS FET.

Abstract: A local oscillator (LO) circuit includes a voltage controlled oscillator (VCO) configured to receive an output of a phase locked loop (PLL) circuit, the VCO coupled to a clock gating circuit configured to generate a VCO output signal (vco_g), a local oscillator (LO) divider configured to receive the VCO output signal (vco_g) and a local oscillator (LO) preset signal, the LO preset signal configured to set the LO divider to a predetermined initial phase, a programmable divider configured to receive a divider signal and the VCO output signal (vco_g) and generate a local oscillator (LO) phase detection trigger signal, Fv, a toggling accumulator coupled to an output of the programmable divider, the toggling accumulator configured to receive the divider signal and the LO phase detection trigger signal, Fv, and generate a counter signal, and a decision logic configured to receive a sample enable signal and the counter signal and adjust the programmable divider based on the sample enable signal and the counter signa

Abstract: Certain aspects of the present disclosure generally relate to techniques and circuits for phase correction, or at least adjustment, of multiple local-oscillator (LO) signals. For example, certain aspects provide an apparatus for phase adjustment. The apparatus generally includes a phase-locked loop (PLL), at least one frequency divider coupled to an output of the PLL, the at least one first frequency divider being external to the PLL, a phase adjustment circuit having an input coupled to an output of the frequency divider, and at least one mixer having an input coupled to at least one output of the phase adjustment circuit.

Abstract: A method includes generating a first signal based on a difference between a first frequency of a first voltage controlled oscillator (VCO) and a second frequency of a second VCO. The method further includes determining a gain of the first VCO at least partially based on the first signal.

Abstract: Certain aspects of the present disclosure provide techniques and apparatus for generating in-phase and quadrature (I/Q) local oscillator (LO) signals that may be synthesized using signals output from a divide-by-odd-number frequency divider (e.g., Div3 or Div5). This may be accomplished by deriving each period of the LO signal from a selected output signal of the frequency divider such that the average phase over multiple LO periods yields desired I/Q LO signals. This operation may save current because a phase interpolation circuit need not be used and moreover, provide I/Q LO signals having equal gain. Certain aspects of the present disclosure also provide a “dummy” LO signal, which may be used to in conjunction with a “dummy load” to present constant load impedance to a low noise amplifier (LNA) during time gaps (periods of an oscillating signal input to the frequency divider) in which the I/Q LO signals are all off.

Abstract: A method, an apparatus, and a computer program product are provided. The apparatus generates LO signals. The apparatus includes a LO generator module and an injection signal generator module coupled together. The LO generator module has a plurality of LO outputs and a plurality of injection signal inputs. The LO module is configured to generate the LO signals on the LO outputs based on injection signals received on the injection signal inputs. The injection signal generator module has a plurality of LO inputs and a plurality of injection signal outputs. The LO inputs are coupled to the LO outputs. The injection signal outputs are coupled to the injection signal inputs. The injection signal generator module is configured to generate injection signals on the injection signal outputs based on the LO signals received on the LO inputs and based on a received VCO signal.

Abstract: A method, an apparatus, and a computer program product are provided. The apparatus generates LO signals. The apparatus includes a LO generator module and an injection signal generator module coupled together. The LO generator module has a plurality of LO outputs and a plurality of injection signal inputs. The LO module is configured to generate the LO signals on the LO outputs based on injection signals received on the injection signal inputs. The injection signal generator module has a plurality of LO inputs and a plurality of injection signal outputs. The LO inputs are coupled to the LO outputs. The injection signal outputs are coupled to the injection signal inputs. The injection signal generator module is configured to generate injection signals on the injection signal outputs based on the LO signals received on the LO inputs and based on a received VCO signal.