Abstract: A semiconductor device includes: a semiconductor device, comprising: a bit line structure including a bit line contact plug, a bit line, and a bit line hard mask that are sequentially stacked over a substrate; a storage node contact plug that is spaced apart from the bit line structure; a conformal spacer that is positioned between the bit line and the storage node contact plug and includes a low-k material; and a seed liner that is positioned between the conformal spacer and the bit line and thinner than the conformal spacer.

Abstract: A composition for strengthening, developing, differentiating, or regenerating muscle, or preventing, ameliorating, or treating muscle loss or muscle fatigue includes a Schizonepeta tenuifolia extract as an effective component. The Schizonepeta tenuifolia extract as an effective component has the effects of restoring the viability of muscle cells, increasing the endurance time on the rotarod performance test, i.e., the holding time without falling off from the rod, compared to the control group, reducing the content of LDH, AST, and ALT in blood, increasing the grip strength, enhancing the expression amount of energy metabolism-related genes in muscle tissues, increasing the density of muscle fibers in muscle tissues, inducing a change in the fibroblast arrangement to have a well-organized structure, and reducing the expression of MuRF1 in muscle tissues, as compared to the control group.

Abstract: Provided are a curcumin nanoparticle complex having a modified particle surface and a method for preparing same. A curcumin nanoparticle complex includes curcumin and phospholipids and has a particle size of less than 1000 nm. A first coating layer containing a cationic material and/or a second coating layer containing an anionic material can be further added.

Abstract: A display apparatus includes a display panel, a memory, a bit-data convertor, a switch, and a gate driver. The display panel includes pixels. Each pixel is connected to one of the data lines and one of the gate lines. The memory stores a plurality of image data corresponding to a frame period. The bit-data convertor determines a plurality of bit data. Each of the bit data corresponds to a degree of change between adjacent image data among the plurality of image data, obtains a sum of the bit data, and outputs the sum of the bit data as a total count bit data value. The switch outputs a first pulse control signal corresponding to the total count bit data value. The gate driver generates a gate signal based on the first pulse control signal, and to output the gate signal to one of the gate lines.

Abstract: A liquid crystal display device, including a display panel including data lines and gate lines intersecting the data lines, a gate driver configured to sequentially apply a scan signal to the gate lines, a data driver configured to apply data voltages corresponding to each gate lines to the data lines, a timing controller configured to control the gate driver and the data driver, a power source supply circuit configured to supply a positive power source and a negative power source, a common voltage feedback circuit configured to receive the positive power source and the negative power source from the power source supply circuit, receive a reference voltage and a common voltage from the display panel, and output an amplified feedback signal corresponding to a voltage level difference between the reference voltage and the common voltage.

Abstract: A memory is provided, which comprises an electrically erasable and programmable read only memory (EEPROM) configured to store an operation system and to be rewritable in response to a write operation signal, an address comparator configured to be connected to Inter Integrated Circuit (I2C) lines and output the write operation signal to the EEPROM in response to an external signal, a digital-to-analog converter (DAC) unit configured to determine whether to connect a DAC resistor and the I2C lines in response to the external signal and a pull-up resistor unit configured to be connected to the I2C lines.

Abstract: Provided herein are a pharmaceutical composition for the prevention and treatment of cancer, including, as an active ingredient, E124 protein or a fragment thereof, or an expression vector including a nucleotide sequence encoding the E124 protein or the fragment thereof, and a method of screening a cancer therapeutic agent candidate.

Abstract: A liquid crystal display device is provided as follows. A display panel having a first aspect ratio includes pixels, scan lines and data lines. The pixels are arranged at intersections of the scanning lines and the data lines. A display panel driver, in a partial mode in which an image having a second aspect ratio different from the first aspect ratio is displayed on a partial region of the display panel for two or more frame periods, supplies scan signals only to a first number of scan lines electrically connected to pixels of the partial region for a first type frame period of the two or more frame periods, and supplies scan signals to the plurality of scan lines for a second type frame period of the two or more frame periods.

Abstract: A display device includes a display panel, a variable gate clock generator and a gate driver. The display panel includes a plurality of pixels coupled to a plurality of data lines and a plurality of gate lines, respectively. The variable gate clock generator generates a first variable gate clock signal and a second variable gate clock signal having respective duty ratios that are varied depending on a brightness of a frame image. The gate driver generates a plurality of gate driving signals for driving the gate lines in response to the first and second variable gate clock signals.

Abstract: A power supply of the present disclosure includes: a power generator that generates a first driving voltage to be supplied to a timing controller; and a voltage compensator that performs feedback of the first driving voltage and generates a feedback voltage according to a voltage difference between the first driving voltage and a first reference voltage supplied from the power generator. In this structure, the power generator generates a second driving voltage by boosting or dropping the first driving voltage to correspond to the feedback voltage, and may supply the second driving voltage to the timing controller.

Abstract: A display apparatus includes a display panel, a memory, a bit-data convertor, a switch, and a gate driver. The display panel includes pixels. Each pixel is connected to one of the data lines and one of the gate lines. The memory stores a plurality of image data corresponding to a frame period. The bit-data convertor determines a plurality of bit data. Each of the bit data corresponds to a degree of change between adjacent image data among the plurality of image data, obtains a sum of the bit data, and outputs the sum of the bit data as a total count bit data value. The switch outputs a first pulse control signal corresponding to the total count bit data value. The gate driver generates a gate signal based on the first pulse control signal, and to output the gate signal to one of the gate lines.

Abstract: The present invention relates to a toughened glass cutting method and a toughened glass cutting apparatus and, more specifically, to a toughened glass cutting method and a toughened glass cutting apparatus for subdividing toughened disk glass into unit glass. To this end, the present invention provides a toughened glass cutting method, characterized by comprising: a crack formation step for forming at least one crack on a cutting line of toughened glass to be cut; and a cutting step for cutting the toughened glass along the cutting line by heating the cutting line of the toughened glass.

Abstract: A method of reducing a time for switching a gate line driving signal of display device having plural gate lines from a level that is less than a full gate-on level to the gate-on level is disclosed. The method may include: during a gate line pre-charging period of a respective gate line, causing the gate line driving signal to be at the full gate-on level; during a corresponding gate line main-charging period that follows the pre-charging period, causing the gate line driving signal of to be at the full gate-on level; and during an interposed period that is interposed between the gate line pre-charging period and its corresponding gate line main-charging period, causing the gate line driving signal to be at an intermediate level that is between the full gate-on level and an opposed gate-off level.

Abstract: A liquid crystal display device, including a display panel including data lines and gate lines intersecting the data lines, a gate driver configured to sequentially apply a scan signal to the gate lines, a data driver configured to apply data voltages corresponding to each gate lines to the data lines, a timing controller configured to control the gate driver and the data driver, a power source supply circuit configured to supply a positive power source and a negative power source, a common voltage feedback circuit configured to receive the positive power source and the negative power source from the power source supply circuit, receive a reference voltage and a common voltage from the display panel, and output an amplified feedback signal corresponding to a voltage level difference between the reference voltage and the common voltage.

Abstract: A memory is provided, which comprises an electrically erasable and programmable read only memory (EEPROM) configured to store an operation system and to be rewritable in response to a write operation signal, an address comparator configured to be connected to Inter Integrated Circuit (I2C) lines and output the write operation signal to the EEPROM in response to an external signal, a digital-to-analog converter (DAC) unit configured to determine whether to connect a DAC resistor and the I2C lines in response to the external signal and a pull-up resistor unit configured to be connected to the I2C lines.

Abstract: A display device includes a display panel, a variable gate clock generator and a gate driver. The display panel includes a plurality of pixels coupled to a plurality of data lines and a plurality of gate lines, respectively. The variable gate clock generator generates a first variable gate clock signal and a second variable gate clock signal having respective duty ratios that are varied depending on a brightness of a frame image. The gate driver generates a plurality of gate driving signals for driving the gate lines in response to the first and second variable gate clock signals.

Abstract: The invention provides a silane compound that includes a hydrophobic group and a silane ester group linked by a hydrophilic group for use as a surface treatment to an inorganic material, such as a pigment, the silane including a hydrophobic group and a silane ester group linked by a hydrophilic group. The invention includes a coated particle including an inorganic material coated with the silane compound(s) and methods of improving the wettability and/or dispersibility of an inorganic material such as a pigment, wherein the method comprises depositing the silane compounds on the surface of a pigment.

Abstract: A method of reducing a time for switching a gate line driving signal of display device having plural gate lines from a level that is less than a full gate-on level to the gate-on level is disclosed. The method may include: during a gate line pre-charging period of a respective gate line, causing the gate line driving signal to be at the full gate-on level; during a corresponding gate line main-charging period that follows the pre-charging period, causing the gate line driving signal of to be at the full gate-on level; and during an interposed period that is interposed between the gate line pre-charging period and its corresponding gate line main-charging period, causing the gate line driving signal to be at an intermediate level that is between the full gate-on level and an opposed gate-off level.

Abstract: A method for anti-stain treatment of fabric is disclosed. The method for anti-stain treatment of fabric includes: immersing fabric in an aqueous solution containing a telomerized perfluoroalkyl acrylate copolymer, and a crosslinking agent, such as an isocyanate crosslinking agent; dehydrating the immersed fabric; drying the dehydrated fabric; heat treating the dried fabric; and coating the heat-treated fabric with a flame retardant, such as an acrylic flame retardant, to provide flame retardancy. The method provides a car seat fabric having superior stain resistance, water repellency and oil repellency without degradation of other properties required for the car seat fabric, such as flame retardancy, lightfastness, frictional coloration, or the like. The method is widely applicable to commercially applicable car seat fabrics, including flat woven, flat tricot, double raschel, or the like.

Abstract: A method for anti-stain treatment of fabric is disclosed. The method for anti-stain treatment of fabric includes: immersing fabric in an aqueous solution containing a telomerized perfluoroalkyl acrylate copolymer, and a crosslinking agent, such as an isocyanate crosslinking agent; dehydrating the immersed fabric; drying the dehydrated fabric; heat treating the dried fabric; and coating the heat-treated fabric with a flame retardant, such as an acrylic flame retardant, to provide flame retardancy. The method provides a car seat fabric having superior stain resistance, water repellency and oil repellency without degradation of other properties required for the car seat fabric, such as flame retardancy, lightfastness, frictional coloration, or the like. The method is widely applicable to commercially applicable car seat fabrics, including flat woven, flat tricot, double raschel, or the like.