Abstract: The disclosure discloses a preparation method and product of carbon fiber reinforced polymer composites with a designable characteristic structure. The method includes: (a) choosing carbon fabrics as raw material, where a predetermined number of the fabrics are selected to deposit the reinforcement phase; (b) coating all carbon fabrics with resin matrix, placing the fabrics layer by layer, where the carbon fabrics with the reinforcement phases are placed in a predetermined layer, meanwhile a micro power supply is placed in a setting layer during the stacking process, then a prefabricated product is obtained; (c) placing the prefabricated product in a vacuum bag then evacuating and sealing, hot pressing the sealed prefabricated product, finally the carbon fiber reinforced polymer composite product in the vacuum bag after hot pressing is successfully manufactured.

Abstract: This application provides a memory, a chip, and a method for storing repair information of the memory. The memory includes a repair circuit that is configured to receive a first signal from a processor and determine to be powered by a first power supply or a second power supply based on a status of the first signal, to store repair information. The repair information is information of the failed bit cells in the memory. The first power supply is zero or in a high impedance state when a system is powered off, and the second power supply is not zero when the system is powered off. The memory further comprises a processing circuit configured to perform communication between the memory and the processor based on the repair information. Therefore, the repair information of the memory can be stored even during power loss.

Abstract: A storage unit includes a latch, and the latch provides a first storage bit. The storage unit further includes a first MOS transistor. A gate of the first MOS transistor is connected to the first storage bit, a source of the first MOS transistor is connected to a first read line, and a drain of the first MOS transistor is connected to a second read line. In a first state, the first read line is a read word line, and the second read line is a read bit line; or in a second state, the second read line is a read word line, and the first read line is a read bit line.

Abstract: A memory and a signal processing method are provided. The memory includes a latch circuit, a decoding circuit, a storage array, a read circuit, and a write circuit. The storage array includes M rows and N columns of bitcells. The latch circuit is configured to receive a first address and a second address. The decoding circuit is configured to: determine a first bitcell based on the first address, and determine a second bitcell based on the second address. The write circuit is configured to: receive data, and write the data into the first bitcell through a first port of the first bitcell. The read circuit is configured to read, through the first port of the first bitcell, data stored in the first bitcell; and is further configured to read, through a second port of the second bitcell, data stored in the second bitcell. Implementing this application can implement 1R1RW.

Abstract: A storage unit includes a latch, and the latch provides a first storage bit. The storage unit further includes a first MOS transistor. A gate of the first MOS transistor is connected to the first storage bit, a source of the first MOS transistor is connected to a first read line, and a drain of the first MOS transistor is connected to a second read line. In a first state, the first read line is a read word line, and the second read line is a read bit line; or in a second state, the second read line is a read word line, and the first read line is a read bit line.

Abstract: A storage unit and a static random access memory (SRAM), where storage unit includes a latch, and the latch provides a first storage bit. The storage unit further includes a first metal-oxide-semiconductor (MOS) transistor. A gate of the first MOS transistor is coupled to the first storage bit, a source of the first MOS transistor is coupled to a first read line, and a drain of the first MOS transistor is coupled to a second read line. In a first state, the first read line is a read word line, and the second read line is a read bit line, or in a second state, the second read line is a read word line, and the first read line is a read bit line. The storage unit according to embodiments of the present invention can implement an exchange between a read word line and a read bit line.

Abstract: A memory and a signal processing method are provided. The memory includes a latch circuit, a decoding circuit, a storage array, a read circuit, and a write circuit. The storage array includes M rows and N columns of bitcells. The latch circuit is configured to receive a first address and a second address. The decoding circuit is configured to: determine a first bitcell based on the first address, and determine a second bitcell based on the second address. The write circuit is configured to: receive data, and write the data into the first bitcell through a first port of the first bitcell. The read circuit is configured to read, through the first port of the first bitcell, data stored in the first bitcell; and is further configured to read, through a second port of the second bitcell, data stored in the second bitcell. Implementing this application can implement 1R1RW.

Abstract: A storage unit and a static random access memory (SRAM), where storage unit includes a latch, and the latch provides a first storage bit. The storage unit further includes a first metal-oxide-semiconductor (MOS) transistor. A gate of the first MOS transistor is coupled to the first storage bit, a source of the first MOS transistor is coupled to a first read line, and a drain of the first MOS transistor is coupled to a second read line. In a first state, the first read line is a read word line, and the second read line is a read bit line, or in a second state, the second read line is a read word line, and the first read line is a read bit line. The storage unit according to embodiments of the present invention can implement an exchange between a read word line and a read bit line.

Abstract: A timing processing method and a circuit for a synchronous SRAM are provided. The method includes: directly inputting an address signal to a wordline decoder for logic decoding; generating various signals by setting various devices in terms of timing; and performing sensitive amplification on data that is input by a memory cell array and is selected by a bitline, and then outputting the data, that is, generating a data output signal. The circuit for a synchronous SRAM includes: a wordline decoder, a timing generator, a wordline controller, a wordline pulse width generator, a memory cell array, and a sense amplifier.

Abstract: A timing processing method and a circuit for a synchronous SRAM are provided. The method includes: directly inputting an address signal to a wordline decoder for logic decoding; generating various signals by setting various devices in terms of timing; and performing sensitive amplification on data that is input by a memory cell array and is selected by a bitline, and then outputting the data, that is, generating a data output signal. The circuit for a synchronous SRAM includes: a wordline decoder, a timing generator, a wordline controller, a wordline pulse width generator, a memory cell array, and a sense amplifier.

Abstract: The invention provides a method and apparatus for searching for data in a memory. The memory includes at least two storage areas, each storage area includes at least two storage blocks, and storage blocks in each storage area are corresponding to each other. The method includes: determining whether a hit storage block that matches with data to be searched for exists in a current storage area; and if it is determined that the hit storage block exists, searching for a storage block corresponding to the hit storage block in a next storage area, so as to determine whether a hit storage block further exists. Accordingly, a storage block corresponding to a missed storage block may execute no operation, thus reducing power consumption.