Patents by Inventor Yunn-Hwa Wang

Yunn-Hwa Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180041211
    Abstract: Sending, receiving and transmitting apparatuses of a dual-power system and a fingerprint recognition system are provided. The dual-power system includes a first power system for providing a first high voltage signal and a first low voltage signal and a second power system for providing a second high voltage signal and a second low voltage signal, and a voltage difference between the first high voltage signal and the first low voltage signal is equal to that between the second high voltage signal and the second low voltage signal. The sending apparatus includes a first detection circuit for outputting a detection signal indicating whether voltages of the first and second low voltage signals are equal; and a first transmission circuit for transmitting an output signal of the dual-power system or provide a first voltage to an output terminal of the sending apparatus, based on the detection signal.
    Type: Application
    Filed: July 27, 2017
    Publication date: February 8, 2018
    Inventors: Yunn-Hwa WANG, Kuet Liong FAM
  • Patent number: 5397936
    Abstract: In an autozero type MOSFET comparator, the spurious current induced by the high frequency input voltage can flow through the resistance of the reset switch to introduce an offset voltage error during the autozero mode. A canceler is used to prevent the spurious current from flowing through the reset switch. A T-network with two series capacitors and a shunt switch is used as the canceler. The spurious current is by-passed by the shunt switch and prevented from flowing through the reset switch placed at the output of the T-network.The spurious current canceler is particularly useful for a sub-ranging ADC, where the comparator is used also as a sample-and-hold circuit to hold the input voltage across the series capacitors by opening all the sampling switches, the reset switch and the shunt switch.
    Type: Grant
    Filed: May 3, 1993
    Date of Patent: March 14, 1995
    Assignee: Industrial Technology Research Institute
    Inventor: Yunn-Hwa Wang
  • Patent number: 5223834
    Abstract: A timing control for precharged digital circuits to avoid spurious error appearing at the output due to the slow pull-down of the precharged node after precharging. A NAND gate is used to delay the precharged node siganl transmitting to the output stage until the precharged node is fully discharged. This timing control circuit is used to prevent any spurious peaking of the output of an analog-to-digital converter using precharged bit lines.
    Type: Grant
    Filed: November 29, 1991
    Date of Patent: June 29, 1993
    Assignee: Industrial Technology Research Institute
    Inventors: Yunn-Hwa Wang, Yung-Peng Hwung, Tien-Yu Wu