Abstract: Various implementations described herein are directed to a device with a voltage-controlled oscillator that receives an enable signal, receives a reset signal, and provides internal pulse signals including one or more coarse internal pulse signals and multiple fine internal pulse signals. The device may have a coarse sampler that receives the one or more coarse internal pulse signal and provides a coarse sampled output signal. The device may have a fine sampler that receives the multiple fine internal pulse signals and provides a fine sampled output signal.

Abstract: Various implementations described herein are directed to a device with a voltage-controlled oscillator that receives an enable signal, receives a reset signal, and provides internal pulse signals including one or more coarse internal pulse signals and multiple fine internal pulse signals. The device may have a coarse sampler that receives the one or more coarse internal pulse signal and provides a coarse sampled output signal. The device may have a fine sampler that receives the multiple fine internal pulse signals and provides a fine sampled output signal.

Abstract: Provided are an electrocardiogram signal parallel analysis apparatus, a mobile terminal incorporating the apparatus, and related methods. The apparatus includes an integrated memory, a central processing unit and a graphic processing unit. The integrated memory includes a first memory and a second memory for being used by the central processing unit and the graphic processing unit respectively, and the central processing unit may access the second memory. The central processing unit performs primary noise reduction on a received electrocardiogram original signal to obtain a primary electrocardiogram signal, and performs abnormal heartbeat classification preliminary screening on characteristic data extracted from the graphic processing unit to obtain suspected abnormal heartbeat data.

Abstract: A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.

Abstract: Provided are an electrocardiogram signal parallel analysis apparatus, a mobile terminal incorporating the apparatus, and related methods. The apparatus includes an integrated memory, a central processing unit and a graphic processing unit. The integrated memory includes a first memory and a second memory for being used by the central processing unit and the graphic processing unit respectively, and the central processing unit may access the second memory. The central processing unit performs primary noise reduction on a received electrocardiogram original signal to obtain a primary electrocardiogram signal, and performs abnormal heartbeat classification preliminary screening on characteristic data extracted from the graphic processing unit to obtain suspected abnormal heartbeat data.

Abstract: The present disclosure provides a GPU-based parallel electrocardiogram signal analysis method, comprising: performing a filtering process of electrocardiogram signals through a long interval artifact removal and a short interval artifact removal; performing a QRS detection of the filtering-processed electrocardiogram signals through an R-wave position extraction, a QRS complex start and end positions extraction and a QRS complex width extraction; performing an abnormal waveform classification of the QRS-detected electrocardiogram signals through template creation; wherein at least one of the long interval artifact removal, the short interval artifact removal, the R-wave position extraction, the QRS complex width extraction and the creation template is performed by a multiple threads at a GPU device side in parallel, any thread being read through its unique index number to process corresponding data.

Abstract: A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.

Abstract: A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.

Abstract: A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.

Abstract: The present disclosure provides a GPU-based parallel electrocardiogram signal analysis method, comprising: performing a filtering process of electrocardiogram signals through a long interval artifact removal and a short interval artifact removal; performing a QRS detection of the filtering-processed electrocardiogram signals through an R-wave position extraction, a QRS complex start and end positions extraction and a QRS complex width extraction; performing an abnormal waveform classification of the QRS-detected electrocardiogram signals through template creation; wherein at least one of the long interval artifact removal, the short interval artifact removal, the R-wave position extraction, the QRS complex width extraction and the creation template is performed by a multiple threads at a GPU device side in parallel, any thread being read through its unique index number to process corresponding data.