Patents by Inventor Yunpeng CAI

Yunpeng CAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10743789
    Abstract: Provided are an electrocardiogram signal parallel analysis apparatus, a mobile terminal incorporating the apparatus, and related methods. The apparatus includes an integrated memory, a central processing unit and a graphic processing unit. The integrated memory includes a first memory and a second memory for being used by the central processing unit and the graphic processing unit respectively, and the central processing unit may access the second memory. The central processing unit performs primary noise reduction on a received electrocardiogram original signal to obtain a primary electrocardiogram signal, and performs abnormal heartbeat classification preliminary screening on characteristic data extracted from the graphic processing unit to obtain suspected abnormal heartbeat data.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: August 18, 2020
    Assignee: SHENZHEN INSTITUTES OF ADVANCED TECHNOLOGY, CHINESE ACADEMY OF SCIENCES
    Inventors: Ye Li, Xiaomao Fan, Yunpeng Cai, Qihang Yao, Yujie Yang
  • Patent number: 10505523
    Abstract: A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: December 10, 2019
    Assignees: ARM Limited, University of Southampton
    Inventors: Anand Savanth, James Edward Myers, Yunpeng Cai, Alexander Stewart Weddell, Tom Kazmierski
  • Publication number: 20190150778
    Abstract: Provided are an electrocardiogram signal parallel analysis apparatus, a mobile terminal incorporating the apparatus, and related methods. The apparatus includes an integrated memory, a central processing unit and a graphic processing unit. The integrated memory includes a first memory and a second memory for being used by the central processing unit and the graphic processing unit respectively, and the central processing unit may access the second memory. The central processing unit performs primary noise reduction on a received electrocardiogram original signal to obtain a primary electrocardiogram signal, and performs abnormal heartbeat classification preliminary screening on characteristic data extracted from the graphic processing unit to obtain suspected abnormal heartbeat data.
    Type: Application
    Filed: November 28, 2017
    Publication date: May 23, 2019
    Inventors: YE LI, XIAOMAO FAN, YUNPENG CAI, QIHANG YAO, YUJIE YANG
  • Patent number: 10258250
    Abstract: The present disclosure provides a GPU-based parallel electrocardiogram signal analysis method, comprising: performing a filtering process of electrocardiogram signals through a long interval artifact removal and a short interval artifact removal; performing a QRS detection of the filtering-processed electrocardiogram signals through an R-wave position extraction, a QRS complex start and end positions extraction and a QRS complex width extraction; performing an abnormal waveform classification of the QRS-detected electrocardiogram signals through template creation; wherein at least one of the long interval artifact removal, the short interval artifact removal, the R-wave position extraction, the QRS complex width extraction and the creation template is performed by a multiple threads at a GPU device side in parallel, any thread being read through its unique index number to process corresponding data.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: April 16, 2019
    Assignee: SHENZHEN INSTITUTES OF ADVANCED TECHNOLOGY CHINESE ACADEMY OF SCIENCES
    Inventors: Ye Li, Xiaomao Fan, Furu Xiang, Yunpeng Cai, Fen Miao
  • Publication number: 20180278244
    Abstract: A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.
    Type: Application
    Filed: May 25, 2018
    Publication date: September 27, 2018
    Inventors: Anand Savanth, James Edward Myers, Yunpeng Cai, Alexander Stewart Weddell, Tom Kazmierski
  • Patent number: 9985613
    Abstract: A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: May 29, 2018
    Assignees: ARM Limited, University of Southampton
    Inventors: Anand Savanth, James Edward Myers, Yunpeng Cai, Alexander Stewart Weddell, Tom Kazmierski
  • Publication number: 20180123571
    Abstract: A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.
    Type: Application
    Filed: October 27, 2016
    Publication date: May 3, 2018
    Inventors: Anand Savanth, James Edward Myers, Yunpeng Cai, Alexander Stewart Weddell, Tom Kazmierski
  • Publication number: 20170105643
    Abstract: The present disclosure provides a GPU-based parallel electrocardiogram signal analysis method, comprising: performing a filtering process of electrocardiogram signals through a long interval artifact removal and a short interval artifact removal; performing a QRS detection of the filtering-processed electrocardiogram signals through an R-wave position extraction, a QRS complex start and end positions extraction and a QRS complex width extraction; performing an abnormal waveform classification of the QRS-detected electrocardiogram signals through template creation; wherein at least one of the long interval artifact removal, the short interval artifact removal, the R-wave position extraction, the QRS complex width extraction and the creation template is performed by a multiple threads at a GPU device side in parallel, any thread being read through its unique index number to process corresponding data.
    Type: Application
    Filed: December 23, 2016
    Publication date: April 20, 2017
    Inventors: Ye LI, Xiaomao FAN, Furu XIANG, Yunpeng CAI, Fen MIAO