Abstract: A method is provided for forming CMOS transistors. The method includes providing a semiconductor substrate having at least one first region and at least one second region; and forming a first gate in the first region and a second gate in the second region. The method also includes forming first offset spacers made of nitrogen-contained material on side surfaces of the first gate and the second gate; and forming dummy spacers on the first offset spacers in the first region and a dummy spacer material layer covering the second gate and the semiconductor substrate in the second region. Further, the method includes forming SiGe stress layers in the semiconductor substrate at both sides of the first gate; and removing the first offset spacers, the dummy spacers and the dummy spacer material layer. Further, the method also includes forming second offset spacers on the first gate and the second gate.

Abstract: A method is provided for forming CMOS transistors. The method includes providing a semiconductor substrate having at least one first region and at least one second region; and forming a first gate in the first region and a second gate in the second region. The method also includes forming first offset spacers made of nitrogen-contained material on side surfaces of the first gate and the second gate; and forming dummy spacers on the first offset spacers in the first region and a dummy spacer material layer covering the second gate and the semiconductor substrate in the second region. Further, the method includes forming SiGe stress layers in the semiconductor substrate at both sides of the first gate; and removing the first offset spacers, the dummy spacers and the dummy spacer material layer. Further, the method also includes forming second offset spacers on the first gate and the second gate.

Abstract: A chip-to-wafer bonding method and a three-dimensional integrated semiconductor device are provided. The method comprises providing a chip and a wafer having a bonding region of the same size and shape as the chip; preparing hydrophilic areas and hydrophobic areas on the chip; preparing in the bonding region hydrophilic areas and hydrophobic areas respectively corresponding to the hydrophilic and hydrophobic areas on the chip; adding a liquid drop onto the hydrophilic areas in the bonding region; and pre-aligning and placing the chip on the bonding region of the wafer, such that the hydrophilic areas on the chip each contacts the corresponding hydrophilic area in the bonding region via the liquid. The sum of perimeters of the hydrophilic areas on the chip is larger than a perimeter of the chip. The sum of perimeters of the hydrophilic areas in the bonding region is larger than a perimeter of the bonding region.

Abstract: A chip-to-wafer bonding method and a three-dimensional integrated semiconductor device are provided. The method comprises providing a chip and a wafer having a bonding region of the same size and shape as the chip; preparing hydrophilic areas and hydrophobic areas on the chip; preparing in the bonding region hydrophilic areas and hydrophobic areas respectively corresponding to the hydrophilic and hydrophobic areas on the chip; adding a liquid drop onto the hydrophilic areas in the bonding region; and pre-aligning and placing the chip on the bonding region of the wafer, such that the hydrophilic areas on the chip each contacts the corresponding hydrophilic area in the bonding region via the liquid. The sum of perimeters of the hydrophilic areas on the chip is larger than a perimeter of the chip. The sum of perimeters of the hydrophilic areas in the bonding region is larger than a perimeter of the bonding region.