Patents by Inventor Yunqi ZHANG

Yunqi ZHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9658207
    Abstract: A microfilter comprising a polymer layer formed from epoxy-based photo-definable dry film, and a plurality of apertures each extending through the polymer layer. A microfilter comprising two or more polymer layers formed from epoxy-based photo-definable dry film, and a plurality of apertures or open areas each extending through the polymer layer. A method of forming a microfilter is also disclosed. The method includes providing a first layer of epoxy-based photo-definable dry film disposed on a substrate, exposing the first layer to energy through a mask to form a pattern, defined by the mask, in the first layer of dry film, forming, from the exposed first layer of dry film, a polymer layer having a plurality of apertures extending therethrough, the plurality of apertures having a distribution defined by the pattern, and removing the polymer layer from the substrate.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: May 23, 2017
    Assignee: CREATV MICROTECH, INC.
    Inventors: Cha-Mei Tang, Yunqi Zhang
  • Patent number: 9484468
    Abstract: The present invention provides a thin film transistor and a manufacturing method thereof, an array substrate, and a display apparatus. The thin film transistor of the present invention comprises a gate, a gate insulation layer, a semiconductor active region, and a source and a drain connected with the semiconductor active region, and further comprises a surface charge transfer layer in contact with the semiconductor active region, the surface charge transfer layer is located above or below the semiconductor active region, and is used for causing the semiconductor active region to generate a large number of holes or electrons therein without changing the lattice structure of the semiconductor active region. In the thin film transistor, charge transfer occurs between the semiconductor active region and the surface charge transfer layer so that the doped semiconductor active region is formed, thus the performance of the thin film transistor is significantly improved.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: November 1, 2016
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yunqi Zhang, Sangsoo Park, Xunze Zhang, Liang Peng, Liumin Yu, Weihua Fang, Yanrui Shen, Liang Xiao, Daowu Huang, Zhiyuan Dong, Longlong Duan, Jian Wang
  • Publication number: 20160027931
    Abstract: The present invention provides a thin film transistor and a manufacturing method thereof, an array substrate, and a display apparatus. The thin film transistor of the present invention comprises a gate, a gate insulation layer, a semiconductor active region, and a source and a drain connected with the semiconductor active region, and further comprises a surface charge transfer layer in contact with the semiconductor active region, the surface charge transfer layer is located above or below the semiconductor active region, and is used for causing the semiconductor active region to generate a large number of holes or electrons therein without changing the lattice structure of the semiconductor active region. In the thin film transistor, charge transfer occurs between the semiconductor active region and the surface charge transfer layer so that the doped semiconductor active region is formed, thus the performance of the thin film transistor is significantly improved.
    Type: Application
    Filed: July 15, 2014
    Publication date: January 28, 2016
    Inventors: Yunqi ZHANG, Sangsoo PARK, Xunze ZHANG, Liang PENG, Liumin YU, Weihua FANG, Yanrui SHEN, Liang XIAO, Daowu HUANG, Zhiyuan DONG, Longlong DUAN, Jian WANG
  • Patent number: 9196683
    Abstract: The present disclosure discloses a method for manufacturing a TFT array substrate, comprising: depositing a gate metal layer, a gate insulating layer, a semiconductor layer and a source-drain electrode layer in this order on a base substrate, performing a first photolithograph process to form a common electrode line, a gate line, a gate electrode, a source electrode, a drain electrode and a channel defined between the source electrode and the drain electrode; depositing a passivation layer, performing a second photolithograph process to form a first via hole and a second via hole in the passivation layer; and depositing a pixel electrode layer and a data line layer in this order, perform a third photolithograph process to form a data line connected to the source electrode through the first via hole and a pixel electrode connected to the drain electrode through the second via hole.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: November 24, 2015
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yunqi Zhang
  • Patent number: 9185392
    Abstract: A moving object to be subject to 3-dimensional rendering is illuminated by a repeated sequence of a number N different two-dimensional structured light patterns. For each illumination, the illuminated object is captured by two spaced apart cameras, thereby creating a series of pairs of two-dimensional images. A set of N adjacent pairs of the two-dimensional images is used to form a single three-dimensional image frame. A moving window of N adjacent pairs of the two-dimensional images provides a train of such three-dimensional image frames. The object may furthered be illuminated by non-structured light whose captured image reflection may be used as an overlay over the three-dimensional rendered object.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: November 10, 2015
    Assignee: Spatial Integrated Systems, Inc.
    Inventors: Ping Zhuang, Yunqi Zhang
  • Publication number: 20150084056
    Abstract: The present disclosure discloses a method for manufacturing a TFT array substrate, comprising: depositing a gate metal layer, a gate insulating layer, a semiconductor layer and a source-drain electrode layer in this order on a base substrate, performing a first photolithograph process to form a common electrode line, a gate line, a gate electrode, a source electrode, a drain electrode and a channel defined between the source electrode and the drain electrode; depositing a passivation layer, performing a second photolithograph process to form a first via hole and a second via hole in the passivation layer; and depositing a pixel electrode layer and a data line layer in this order, perform a third photolithograph process to form a data line connected to the source electrode through the first via hole and a pixel electrode connected to the drain electrode through the second via hole.
    Type: Application
    Filed: December 5, 2014
    Publication date: March 26, 2015
    Inventor: Yunqi ZHANG
  • Patent number: 8987743
    Abstract: The present disclosure discloses a method for manufacturing a TFT array substrate, comprising: depositing a gate metal layer, a gate insulating layer, a semiconductor layer and a source-drain electrode layer in this order on a base substrate, performing a first photolithograph process to form a common electrode line, a gate line, a gate electrode, a source electrode, a drain electrode and a channel defined between the source electrode and the drain electrode; depositing a passivation layer, performing a second photolithograph process to form a first via hole and a second via hole in the passivation layer; and depositing a pixel electrode layer and a data line layer in this order, perform a third photolithograph process to form a data line connected to the source electrode through the first via hole and a pixel electrode connected to the drain electrode through the second via hole.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: March 24, 2015
    Assignees: Boe Technology Group Co., Ltd., Hefei Boe Optoelectroncis Technology Co., Ltd.
    Inventor: Yunqi Zhang
  • Publication number: 20140322743
    Abstract: A microfilter comprising a polymer layer formed from epoxy-based photo-definable dry film, and a plurality of apertures each extending through the polymer layer. A microfilter comprising two or more polymer layers formed from epoxy-based photo-definable dry film, and a plurality of apertures or open areas each extending through the polymer layer. A method of forming a microfilter is also disclosed. The method includes providing a first layer of epoxy-based photo-definable dry film disposed on a substrate, exposing the first layer to energy through a mask to form a pattern, defined by the mask, in the first layer of dry film, forming, from the exposed first layer of dry film, a polymer layer having a plurality of apertures extending therethrough, the plurality of apertures having a distribution defined by the pattern, and removing the polymer layer from the substrate.
    Type: Application
    Filed: November 21, 2012
    Publication date: October 30, 2014
    Applicant: Creatv Microtech, Inc.
    Inventors: Cha-Mei Tang, Yunqi Zhang
  • Publication number: 20140312348
    Abstract: The present disclosure discloses a method for manufacturing a TFT array substrate, comprising: depositing a gate metal layer, a gate insulating layer, a semiconductor layer and a source-drain electrode layer in this order on a base substrate, performing a first photolithograph process to form a common electrode line, a gate line, a gate electrode, a source electrode, a drain electrode and a channel defined between the source electrode and the drain electrode; depositing a passivation layer, performing a second photolithograph process to form a first via hole and a second via hole in the passivation layer; and depositing a pixel electrode layer and a data line layer in this order, perform a third photolithograph process to form a data line connected to the source electrode through the first via hole and a pixel electrode connected to the drain electrode through the second via hole.
    Type: Application
    Filed: July 3, 2014
    Publication date: October 23, 2014
    Inventor: Yunqi ZHANG
  • Patent number: 8823001
    Abstract: The present disclosure discloses a method for manufacturing a TFT array substrate, comprising: depositing a gate metal layer, a gate insulating layer, a semiconductor layer and a source-drain electrode layer in this order on a base substrate, performing a first photolithograph process to form a common electrode line, a gate line, a gate electrode, a source electrode, a drain electrode and a channel defined between the source electrode and the drain electrode; depositing a passivation layer, performing a second photolithograph process to form a first via hole and a second via hole in the passivation layer; and depositing a pixel electrode layer and a data line layer in this order, perform a third photolithograph process to form a data line connected to the source electrode through the first via hole and a pixel electrode connected to the drain electrode through the second via hole.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: September 2, 2014
    Assignees: Boe Technology Group Co., Ltd., Hefei Boe Optoelectronics Technology Co., Ltd.
    Inventor: Yunqi Zhang
  • Publication number: 20140132734
    Abstract: A moving object to be subject to 3-dimensional rendering is illuminated by a repeated sequence of a number N different two-dimensional structured light patterns. For each illumination, the illuminated object is captured by two spaced apart cameras, thereby creating a series of pairs of two-dimensional images. A set of N adjacent pairs of the two-dimensional images is used to form a single three-dimensional image frame. A moving window of N adjacent pairs of the two-dimensional images provides a train of such three-dimensional image frames. The object may furthered be illuminated by non-structured light whose captured image reflection may be used as an overlay over the three-dimensional rendered object.
    Type: Application
    Filed: November 12, 2012
    Publication date: May 15, 2014
    Applicant: Spatial Intergrated Sytems, Inc.
    Inventors: Ping Zhuang, Yunqi Zhang
  • Publication number: 20130330721
    Abstract: A microfilter comprising a polymer layer formed from photo-definable dry film, and a plurality of apertures each extending through the polymer layer. A microfilter comprising two or more polymer layers formed from photo-definable dry film, and a plurality of apertures or open areas each extending through the polymer layer. Methods of forming apertures in one or more layers of photo-definable dry film are also disclosed. Filter holder designs and methods appropriate to hold microfilters to collect the rare cells and to perform of assays in the filter holder are provided. Microfiltration chip designs and methods appropriate to collect the rare cells and to perform assays in the microfluidic chips are provided. The invention also describes the use of the microfilter, filter holder and microfilter chips to collect rare cells from body fluids and perform assays, and these rare cells can be used for medical and biological research applications.
    Type: Application
    Filed: March 29, 2013
    Publication date: December 12, 2013
    Applicant: Creatv MicroTech, Inc.
    Inventors: Cha-Mei Tang, Yunqi Zhang
  • Publication number: 20120313101
    Abstract: The present disclosure discloses a method for manufacturing a TFT array substrate, comprising: depositing a gate metal layer, a gate insulating layer, a semiconductor layer and a source-drain electrode layer in this order on a base substrate, performing a first photolithograph process to form a common electrode line, a gate line, a gate electrode, a source electrode, a drain electrode and a channel defined between the source electrode and the drain electrode; depositing a passivation layer, performing a second photolithograph process to form a first via hole and a second via hole in the passivation layer; and depositing a pixel electrode layer and a data line layer in this order, perform a third photolithograph process to form a data line connected to the source electrode through the first via hole and a pixel electrode connected to the drain electrode through the second via hole.
    Type: Application
    Filed: June 8, 2012
    Publication date: December 13, 2012
    Applicants: HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Yunqi ZHANG