Abstract: A method of improving mask data used in fabrication of a semiconductor device includes, in part, setting a threshold value associated with a defect based on stochastic failure rate of the defect, performing a first optimal proximity correction (OPC) of the mask data using nominal values of mask pattern contours, identifying locations within the first OPC mask data where stochastically determined mask pattern contours may lead to the defect, placing check figures on the identified locations to enable measurement of distances between the stochastically determined mask pattern contours, and performing a second OPC of the first OPC mask data so as to cause the measured distances to be greater than the threshold value.

Abstract: A method of improving mask data used in fabrication of a semiconductor device includes, in part, setting a threshold value associated with a defect based on stochastic failure rate of the defect, performing a first optimal proximity correction (OPC) of the mask data using nominal values of mask pattern contours, identifying locations within the first OPC mask data where stochastically determined mask pattern contours may lead to the defect, placing check figures on the identified locations to enable measurement of distances between the stochastically determined mask pattern contours, and performing a second OPC of the first OPC mask data so as to cause the measured distances to be greater than the threshold value.

Abstract: Embodiments of the present invention provide systems and techniques for determining the effect of process variations. During operation, the system can receive a layout which includes multiple instances of a pattern. Next, the system can correct the pattern instances using different photolithography process models which model the photolithography process at different exposure and focus conditions. Next, the corrected layout can be printed on a wafer. The system can then perform electrical tests on the wafer, or it can measure the critical dimensions of the features on the wafer. The yield loss or the exposure-focus matrix can then be generated by using the test data or the measurement data.

Abstract: Embodiments of the present invention provide systems and techniques for determining the effect of process variations. During operation, the system can receive a layout which includes multiple instances of a pattern. Next, the system can correct the pattern instances using different photolithography process models which model the photolithography process at different exposure and focus conditions. Next, the corrected layout can be printed on a wafer. The system can then perform electrical tests on the wafer, or it can measure the critical dimensions of the features on the wafer. The yield loss or the exposure-focus matrix can then be generated by using the test data or the measurement data.

Abstract: A method comprises the steps of: (a) simulating on a processor a fabrication of a plurality of layout patterns by a lithographic process; (b) determining sensitivities of the layout patterns to a plurality of parameters based on the simulation; (c) using the sensitivities to calculate deviations of the patterns across a range of each respective one of the parameters; and (d) selecting ones of the patterns having maximum or near-maximum deviations to be used as test patterns.

Abstract: A method comprises the steps of: (a) simulating on a processor a fabrication of a plurality of layout patterns by a lithographic process; (b) determining sensitivities of the layout patterns to a plurality of parameters based on the simulation; (c) using the sensitivities to calculate deviations of the patterns across a range of each respective one of the parameters; and (d) selecting ones of the patterns having maximum or near-maximum deviations to be used as test patterns.

Abstract: A method of fabrication an alignment mark in a semiconductor device. The method uses one mask to that has two functions (1) a reverse active areas mask to remove the oxide from over active areas in the device areas and (2) an alignment mark open mask that removes the oxide from over the alignment mark area. The mask improves chemical-mechanical polish performance in the cell areas by removing the oxide over the active areas. Another key feature of the invention is the spacing of the alignment mark trenches that ensures that the step distance between the top of the second insulating layer in the alignment mark trench and the top surface of the substrate is greater than 2000 Å. This insures that the alignment marks are readable.

Abstract: A method of patterning a gate electrode comprising the following steps. A semiconductor structure, with an upper silicon layer, and having an active area is provided. A sacrificial oxide layer overlies the semiconductor structure, a first polysilicon layer overlies the sacrificial silicon oxide layer, and a silicon nitride layer overlies the polysilicon layer. The nitride, first poly, and sacrificial oxide layers are patterned to form a gate conductor opening within the active area. A gate oxide layer is grown over the semiconductor structure within the gate conductor opening an oxide sidewall spacers are grown on the first polysilicon sidewalls. A second polysilicon layer is deposited over the structure, filling the gate conductor opening. The second polysilicon layer is polished to remove the excess of the second polysilicon layer from the nitride layer, forming a polysilicon gate conductor within the gate conductor opening and over the gate oxide layer.