Abstract: The present disclosure discloses a pixel structure, an array substrate and a display panel. The pixel structure includes a first data line; a first gate line and a second gate line; a first pixel unit and a second pixel unit. The first pixel units and second pixel units arranged along a second direction; a first pixel electrode relative to the second pixel electrode is close to the first data line, a first thin film transistor and second thin film transistors are arranged close to the first data line; first connecting trace is set between the first drain electrode and the first pixel electrode, a second connecting trace is set between the second drain electrode and the second pixel electrode to make a capacitance of the first pixel unit matching with a capacitance of the second pixel unit.

Abstract: Disclosed are a display panel and display apparatus. The display panel is divided into a display region and a peripheral region. The display panel includes: a first substrate; a second substrate arranged opposite to the first substrate; an alignment layer at least formed in the display region; and a sealing layer connecting the first substrate to the second substrate. The display panel is provided with a conducting wire group including at least one conducting wire, and the conducting wire includes a notch. The display panel includes at least one signal line. The signal line penetrates through the notch in the conducting wire to be connected to the display region. The signal line includes a first line segment and a second line segment communicated with each other. An included angle is formed between the second line segment and the first line segment which are bent relative to each other.

Abstract: The present application discloses a gate driver circuit of a display panel, a driving method therefor and a display circuit. The gate driver circuit of a display panel includes a multi-stage cascaded shift register, where an any-stage shift register includes: a charging circuit, a pull-down circuit for controlling to pull down a potential of an output terminal of the charging circuit to a low level in a non-scanning time, and an output control circuit electrically coupled to the output terminal of the charging circuit for receiving an initial gate scanning signal; the output control circuit is connected to an enable signal and controls the output of the gate scanning signal according to the enable signal.

Abstract: The present disclosure discloses a pixel structure, an array substrate and a display panel. The pixel structure includes a first data line; a first gate line and a second gate line; a first pixel unit and a second pixel unit. The first pixel units and second pixel units arranged along a second direction; a first pixel electrode relative to the second pixel electrode is close to the first data line, a first thin film transistor and second thin film transistors are arranged close to the first data line; first connecting trace is set between the first drain electrode and the first pixel electrode, a second connecting trace is set between the second drain electrode and the second pixel electrode to make a capacitance of the first pixel unit matching with a capacitance of the second pixel unit.

Abstract: The present application discloses a gate driver circuit of a display panel, a driving method therefor and a display circuit. The gate driver circuit of a display panel includes a multi-stage cascaded shift register, where an any-stage shift register includes: a charging circuit, a pull-down circuit for controlling to pull down a potential of an output terminal of the charging circuit to a low level in a non-scanning time, and an output control circuit electrically coupled to the output terminal of the charging circuit for receiving an initial gate scanning signal; the output control circuit is connected to an enable signal and controls the output of the gate scanning signal according to the enable signal.

Abstract: A display panel, and the display panel includes an array substrate, a counter substrate, a plurality of active switches, a shift register, a plurality of first testing pads, a plurality of second testing pads, and a tester; an input of the tester is connected to the plurality of first testing pads, an output of the tester is connected to the plurality of second testing pads. Thereby the shift register can be directly detected without pry up the panel, the circuit on the array substrate can be prevented from damaging, which can contribute to the analysis and improvement of the circuit issue.

Abstract: The present application discloses a drive circuit of a display panel and a driving method. The display panel includes a display region, a non-display region, and a drive circuit. The display region includes a scan line and a data line. The non-display region includes a gate drive circuit. The drive circuit includes an alignment control line and an active switch.

Abstract: This application discloses a display panel and a display apparatus. The display panel includes a display area, a seal, a first metal wire, a signal line, a channel and a retaining wall. The seal is correspondingly arranged in a nondisplay area of the display panel. The first metal wire is correspondingly arranged between the display area and the seal. The signal line bridges over the first metal wire and is fed into the display area. The channel is located at a bridging connection position of the first metal wire and the signal line. The retaining wall is arranged at a position corresponding to the channel, beside the first metal wire.

Abstract: The color film substrate includes a base substrate and a plurality of pixel units. Each of the pixel units includes a first color resist, a second color resist, a third color resist, and a fourth color resist. The fourth color resist includes a first secondary color resist, a second secondary color resist, and a third secondary color resist. Areas of the first secondary color resist, the second secondary color resist, and the third secondary color resist are equal. The first secondary color resist and the first color resist are made of the same material, the second secondary color resist and the second color resist are made of the same material, and the third secondary color resist and the third color resist are made of the same material.

Abstract: Disclosed is an array substrate including a first substrate, a first conductive layer, a first passivation layer, a second conductive layer, a second passivation layer, a first electrode layer, a liquid crystal layer, a second electrode layer, and a second substrate in order from bottom to top. The first conductive layer includes a plurality of first traces, the second conductive layer includes a plurality of second traces, and the respective plurality of first traces are connected to the corresponding plurality of second traces through traces of the first electrode layer. Each of the plurality of first traces is provided with a target area and a projection of each of the plurality of second traces on a corresponding connected first trace is located in a corresponding target area to reduce a load of a gate drive circuit and a capacitance between panels.

Abstract: Disclosed is an array substrate including a first substrate, a first conductive layer, a first passivation layer, a second conductive layer, a second passivation layer, a first electrode layer, a liquid crystal layer, a second electrode layer, and a second substrate in order from bottom to top. The first conductive layer includes a plurality of first traces, the second conductive layer includes a plurality of second traces, and the respective plurality of first traces are connected to the corresponding plurality of second traces through traces of the first electrode layer. Each of the plurality of first traces is provided with a target area, and a projection of each of the plurality of second traces on a corresponding connected first trace is located in a corresponding target area to reduce a load of a gate drive circuit and a capacitance between panels.

Abstract: The present disclosure is related to a display panel and a method for manufacturing the same. The display panel comprises a first substrate, a second substrate disposed in parallel with the first substrate, a light shielding layer disposed on the first substrate and defined a plurality of pixel areas, a color filter layer disposed on the plurality of pixel areas, the color filter layer including a first colored resist layer, a second colored resist layer, a third colored resist layer and a fourth colored resist layer, a transparent electrode layer disposed on the color filter layer, and wherein the fourth colored resist layer comprises a plurality of different colored resistor materials sequentially stacked from bottom to top.

Abstract: The present disclosure provides a display panel and a display device, the display panel includes a first substrate, the first substrate defines a photoresist layer; a second substrate, the second substrate defines an identification region, a surface of the first substrate having the photoresist layer faces a surface of the second substrate having the identification region; and a frame glue, the frame glue is defined between the first substrate and the second substrate, and the frame glue encloses a space between the first substrate and the second substrate to form a filling area, and the identification region is defined at the outside of the frame glue; the photoresist layer defines an anti-overflow groove located at an area between the identification region and the frame glue.

Abstract: A display panel, and the display panel includes an array substrate, a counter substrate, a plurality of active switches, a shift register, a plurality of first testing pads, a plurality of second testing pads, and a tester; an input of the tester is connected to the plurality of first testing pads, an output of the tester is connected to the plurality of second testing pads. Thereby the shift register can be directly detected without pry up the panel, the circuit on the array substrate can be prevented from damaging, which can contribute to the analysis and improvement of the circuit issue.

Abstract: This application discloses a display panel and a display apparatus. The display panel includes a display area, a seal, a first metal wire, a signal line, a channel and a retaining wall. The seal is correspondingly arranged in a nondisplay area of the display panel. The first metal wire is correspondingly arranged between the display area and the seal. The signal line bridges over the first metal wire and is fed into the display area. The channel is located at a bridging connection position of the first metal wire and the signal line. The retaining wall is arranged at a position corresponding to the channel, beside the first metal wire.

Abstract: Disclosed are a display panel and display apparatus. The display panel is divided into a display region and a peripheral region. The display panel includes: a first substrate; a second substrate arranged opposite to the first substrate; an alignment layer at least formed in the display region; and a sealing layer connecting the first substrate to the second substrate. The display panel is provided with a conducting wire group including at least one conducting wire, and the conducting wire includes a notch. The display panel includes at least one signal line. The signal line penetrates through the notch in the conducting wire to be connected to the display region. The signal line includes a first line segment and a second line segment communicated with each other. An included angle is formed between the second line segment and the first line segment which are bent relative to each other.

Abstract: The present disclosure provides a display panel and a display device, the display panel includes a frame glue, an alignment mark, and a blocking wall, and the blocking wall is defined between the alignment mark and the frame glue.

Abstract: The present disclosure provides a display panel and a display device, the display panel includes a first substrate, the first substrate defines a photoresist layer; a second substrate, the second substrate defines an identification region, a surface of the first substrate having the photoresist layer faces a surface of the second substrate having the identification region; and a frame glue, the frame glue is defined between the first substrate and the second substrate, and the frame glue encloses a space between the first substrate and the second substrate to form a filling area, and the identification region is defined at the outside of the frame glue; the photoresist layer defines an anti-overflow groove located at an area between the identification region and the frame glue.

Abstract: The present disclosure provides a display panel and a display device, the display panel includes a frame glue, an alignment mark, and a blocking wall, and the blocking wall is defined between the alignment mark and the frame glue.