Abstract: A display substrate includes a substrate and a gate driving circuit provided on the substrate; the gate driving circuit includes: a frame start signal line, a clock signal line, an inverted clock signal line, a first level signal line, a second level signal line, and a plurality of shift register units. The plurality of transistors at least include a first transistor, a second transistor, and a third transistor, active layers of the first, second and third transistors are formed by a continuous first semiconductor layer, the first semiconductor layer extends along a first direction; the first semiconductor layer includes at least three channel portions corresponding to the first transistor, the second transistor and the third transistor, and a conductive portion provided between adjacent channel portions, transistors corresponding to the adjacent channel portions are coupled to each other through a corresponding conductive portion.

Abstract: A display substrate is disclosed, including a display area and a non-display area. The non-display area has a gate drive circuit including multiple cascaded shift register units. A shift register unit includes an input control circuit and an output circuit. The input control circuit is electrically connected to a clock signal line group, a first power supply line, a second power supply line and an output circuit, the output circuit is electrically connected to the first power supply line and a second power supply line. The input control circuit at least includes an input circuit and a first control circuit. The clock signal line group, the second power supply line, the input control circuit, the output circuit and the first power supply line are arranged sequentially along a first direction. The input circuit is located between the second power supply line and the first control circuit in the first direction.

Abstract: A display panel, a driving method, and a display device. The display panel includes: a base substrate, subpixels, driving lines, data lines, a gate driving circuit including clock signal lines and shift register units arranged in extension direction of clock signal lines. The clock signal lines is divided into clock signal line groups; the shift register units is divided into register unit groups; the shift register units in same register unit group are cascaded, adjacent two of shift register units in the extension direction are in different register unit groups; one register unit group corresponds to one clock signal line group; the gate of an input transistor is connected to a clock signal line in a corresponding clock signal line group, the second pole of input transistor is connected to the gate of an output transistor; the second pole of output transistor is connected to at least one driving line.

Abstract: A display substrate includes a source-drain metal layer and a common electrode layer. A pattern of the source-drain metal layer includes a power supply voltage line; the power supply voltage line includes a wire inlet portion; the display substrate further includes a barrier wall, there is a gap between an orthographic projection of the barrier wall on the base substrate and an orthographic projection of the effective display area on the base substrate. The wire inlet portion includes a first part and a second part; an orthographic projection of the first part on the base substrate and an orthographic projection of the gap on the base substrate at least partially overlap; the second part is located at a side of the barrier wall away from the effective display area and located between the barrier wall and the binding area, and used for receiving power supply voltage signal.

Abstract: The pixel circuit includes: a light emitting module configured to emit light; a driving module configured to drive the light emitting module to emit light according to a driving voltage during a light emitting stage; a storage module configured to maintain the driving voltage and to provide the driving voltage to the driving module during the light emitting stage; a first transistor, a first electrode of the first transistor being connected to a position where the driving module receives the driving voltage, and a second electrode of the first transistor being not directly connected to a signal source; a second transistor, a first electrode of the second transistor being connected to the first electrode of the first transistor, wherein a structure to which a second electrode of the second transistor is connected is different from a structure to which the second electrode of the first transistor is connected.

Abstract: A pixel circuit includes a data writing sub-circuit, a driving sub-circuit, and one or more potential maintenance sub-circuits. The data writing sub-circuit is coupled to at least a first voltage signal terminal, a data signal terminal, a first scan signal terminal and a first node, and writes a data signal provided by the data signal terminal into the first node under control of at least a first scan signal provided by the first scan signal terminal. The driving sub-circuit is coupled to the first node, a second node and a third node, and creates a path between the second node and the third node under control of a potential at the first node. A potential maintenance sub-circuit is coupled to a circuit node and a reference signal terminal, and maintains a potential at the circuit node through a reference signal provided by the reference signal terminal.

Abstract: The present disclosure provides a shift register including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor and an impedance transistor; the second transistor has a first electrode coupled to a second node; the third transistor has a first electrode coupled to a first power terminal and a second electrode coupled to the second node; the fifth transistor has a control electrode coupled to a third node; and the impedance transistor has a control electrode coupled to the first power terminal, a first electrode coupled to the second node, and a second electrode coupled to the third node.

Abstract: A display panel, a driving method, and a display device. The display panel includes: a base substrate, subpixels, driving lines, data lines, a gate driving circuit including clock signal lines and shift register units arranged in extension direction of clock signal lines. The clock signal lines is divided into clock signal line groups; the shift register units is divided into register unit groups; the shift register units in same register unit group are cascaded, adjacent two of shift register units in the extension direction are in different register unit groups; one register unit group corresponds to one clock signal line group; the gate of an input transistor is connected to a clock signal line in a corresponding clock signal line group, the second pole of input transistor is connected to the gate of an output transistor; the second pole of output transistor is connected to at least one driving line.

Abstract: A display substrate and a display apparatus are provided, and the display substrate includes a pixel circuit with a light emitting module configured to emit light; a driving module configured to drive the light emitting module to emit light based on a driving voltage in a luminescence stage; a storage module configured to maintain and provide the driving voltage to the driving module in the luminescence stage; a first transistor, having a first electrode coupled to a position from which the driving module acquires the driving voltage; a second transistor, having a first electrode coupled to the first electrode of the first transistor, and a second electrode being not directly coupled to a signal source; and a voltage stabilizing capacitor, having a first electrode coupled to the second electrode of the second transistor, and a second electrode coupled to a constant voltage signal source.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate, multiple sub-pixels, multiple data lines, a test circuit, multiple data leads, at least one test pad, and at least one first test signal line. The multiple data lines are electrically connected to the multiple sub-pixels, and configured to provide data signals to the multiple sub-pixels. The multiple data leads are electrically connected to the multiple data lines and the test circuit. At least one test pad is located on at least one side of the test circuit. The at least one first test signal line is electrically connected to at least one test pad and the test circuit, and includes at least two conductive layers connected in parallel and electrically connected to each other.

Abstract: Disclosed are a pixel circuit, a driving method thereof, a display panel and a display apparatus, relating to the technical field of display. The pixel circuit comprises a drive transistor, a data writing module, a compensation adjustment module and a first reset module. A gate, a first electrode and a second electrode of the drive transistor are respectively connected with a first node, a second node and a third node; the data writing module is connected with a first scanning control signal terminal, a data signal terminal and the second node; the compensation adjustment module is connected with a second scan control signal terminal, the first node and the third node; the first reset module is connected with a first reset control signal terminal, the first node and a first initialization signal terminal.

Abstract: An array substrate and a display device are provided. The array substrate includes: a base substrate, a planarization layer, a package layer, a first barrier wall, and a plurality of first transmission lines. The first barrier wall is in a peripheral region and includes a first barrier wall portion extending along a first direction; and the plurality of first transmission lines are in the peripheral region and at a side of the package layer away from the base substrate. The package layer includes an organic package layer, the planarization layer includes a first edge portion extending along the first direction, and an orthographic projection of at least one of the plurality of first transmission lines on the base substrate is located at a side of the orthographic projection of the first edge portion on the base substrate away from the display region.

Abstract: A pixel circuit includes a driving sub-circuit coupled to a first node, a second node and a third node, a compensation sub-circuit coupled to the first node, the third node and a first scan signal terminal, an adjustment sub-circuit, and a writing sub-circuit. The compensation sub-circuit includes a first transistor group, and the first transistor group includes at least two first transistors connected in series. A fourth node is formed between a second electrode of a first first transistor and a first electrode of a second first transistor. The adjustment sub-circuit is coupled to the fourth node and at least one control terminal. The adjustment sub-circuit is configured to, in light-emitting phases, adjust a voltage of the fourth node under a control of a signal from the at least one control terminal, so as to reduce a voltage difference between the fourth node and the first node.

Abstract: A display substrate includes at least one scan driving circuit. The scan driving circuit includes a first voltage signal line, a second voltage signal line, a third voltage signal line, and shift registers. A shift register includes: first and second transistors disposed between the first voltage signal line and the second voltage signal line, third and fourth transistors disposed between the second voltage signal line and the third voltage signal line, at least one first scan signal line electrically connected to a first output terminal, and at least one second scan signal line electrically connected to a second output terminal. A second electrode of the first transistor and a second electrode of the second transistor are both electrically connected to the first output terminal; a second electrode of the third transistor and a second electrode of the fourth transistor are both electrically connected to a second output terminal.

Abstract: A display substrate and a display apparatus are disclosed. The display substrate includes: a base substrate including a first and second display regions; a light transmittance of the first display region is greater than that of the second display region; first sub-pixels in the first display region. At least one first sub-pixel includes a first pixel circuit and a first light emitting device; the first pixel circuit includes a storage capacitor and a driving transistor; and a data writing sub-circuit configured to write a data voltage signal to a gate electrode of the driving transistor in response to a first and second scan signals; a reset sub-circuit configured to provide an initialization voltage signal to a first electrode of the first light emitting device in response to the second scan signal; and a luminescent control sub-circuit configured to transmit a driving current to the first light emitting device.

Abstract: The pixel circuit includes: a light emitting module configured to emit light; a driving module configured to drive the light emitting module to emit light according to a driving voltage during a light emitting stage; a storage module configured to maintain the driving voltage and to provide the driving voltage to the driving module during the light emitting stage; a first transistor, a first electrode of the first transistor being connected to a position where the driving module receives the driving voltage, and a second electrode of the first transistor being not directly connected to a signal source; a second transistor, a first electrode of the second transistor being connected to the first electrode of the first transistor, wherein a structure to which a second electrode of the second transistor is connected is different from a structure to which the second electrode of the first transistor is connected.

Abstract: A display panel and a display device, relate to the technical field of display technology. The present disclosure disposes a plurality of subpixel on a substrate, each subpixel comprises a compensating transistor, a drive transistor, a storage capacitance and a first initialization signal line, a first active pattern of the compensating transistor includes a first active section, a second active section and a third active section, the second active section extends along a first direction, and extension directions of the first active section and the third active section intersect with the first direction; the first initialization signal line extends along the first direction, and an overlapping area exists between an orthogonal projection of the first initialization signal line on the substrate and an orthogonal projection of the second active section on the substrate, the first initialization signal line overlaps with the first active pattern directly to form a coupling capacitance.

Abstract: A display substrate and a manufacturing method therefor, and a display device are provided. The display substrate includes a drive circuit layer disposed on a substrate, the drive circuit layer includes a plurality of circuit units, at least one circuit unit includes a pixel drive circuit, a first power supply line providing a power supply signal to the pixel drive circuit, a data signal line providing a data signal to the pixel drive circuit, and a data fan-out line connected with the data signal line; at least a portion of the first power supply line, the data signal line, and the data fan-out line extends along a second direction and is arranged at intervals along a first direction, at least a portion of the data fan-out line is disposed between the first power supply line and the data signal line, the first direction intersects with the second direction.

Abstract: A display panel and a display apparatus are disclosed. The display panel includes: a display region, including M first display regions sequentially disposed along a first direction, and a non-display region, including M first GOA circuits and M clock signal line groups; a first display region includes multiple first signal lines sequentially disposed along the first direction and extending along a second direction intersecting with the first direction, a clock signal line group includes multiple clock signal lines, signals of at least two clock signal lines respectively in at least two clock signal line groups are same; a first GOA circuit includes multiple first GOA units, multiple first GOA units in an m-th first GOA circuit are connected with at least one clock signal line in an m-th clock signal line group, and are connected with multiple first signal lines in an m-th first display region in one-to-one correspondence.

Abstract: Provided is a pixel circuit. In the pixel circuit, a data write circuit may transmit a data signal to a first node; a compensation circuit may adjust a potential of a second node and a potential of a third node based on a gate drive signal; a first reset circuit may transmit a first initial power supply signal to the third node; a drive circuit may transmit a drive signal to the second node based on the potential of the third node and a potential of the first node; and a second reset circuit may transmit a second initial power supply signal to a first electrode of a light-emitting element.