Patents by Inventor Yunsup LEE
Yunsup LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11922101Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.Type: GrantFiled: March 20, 2023Date of Patent: March 5, 2024Assignee: SiFive, Inc.Inventors: Yunsup Lee, Richard Xia, Derek Pappas, Mark Nugent, Henry Cook, Wesley Waylon Terpstra, Pin Hung Chen
-
Patent number: 11748536Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.Type: GrantFiled: November 27, 2019Date of Patent: September 5, 2023Assignee: SiFive, Inc.Inventors: Yunsup Lee, Michael Cave
-
Publication number: 20230237217Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.Type: ApplicationFiled: March 20, 2023Publication date: July 27, 2023Inventors: Yunsup Lee, Richard Xia, Derek Pappas, Mark Nugent, Henry Cook, Wesley Waylon Terpstra, Pin Hung Chen
-
Publication number: 20230195980Abstract: Systems and methods are disclosed for integrated circuit design using integrated circuit shells. For example, a system may generate an integrated circuit core design expressed in a hardware description language. The integrated circuit core design may express circuitry that describes one or more functions to be included in an application specific integrated circuit (ASIC). The one or more functions may have connection points providing first inputs and outputs to the one or more functions. The system may query an integrated circuit shell expressed in a hardware description language. The integrated circuit shell may express circuitry that describes a limited set of pads to be implemented in the ASIC. The limited set of pads may provide second inputs and outputs to the integrated circuit. The query may determine availability of pads of the limited set of pads to connect to the connection points of the one or more functions.Type: ApplicationFiled: November 23, 2022Publication date: June 22, 2023Inventors: Ryan Macdonald, Erik Arthur Daine, Wesley Waylon Terpstra, Yunsup Lee
-
Patent number: 11610036Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.Type: GrantFiled: June 28, 2021Date of Patent: March 21, 2023Assignee: SiFive, Inc.Inventors: Yunsup Lee, Richard Xia, Derek Pappas, Mark Nugent, Henry Cook, Wesley Waylon Terpstra, Pin Hung Chen
-
Publication number: 20220050946Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.Type: ApplicationFiled: November 27, 2019Publication date: February 17, 2022Inventors: Yunsup LEE, Michael CAVE
-
Publication number: 20210365609Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.Type: ApplicationFiled: June 28, 2021Publication date: November 25, 2021Inventors: Yunsup Lee, Richard Xia, Derek Pappas, Mark Nugent, Henry Cook, Wesley Waylon Terpstra, Pin Hung Chen
-
Patent number: 11048838Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.Type: GrantFiled: August 1, 2019Date of Patent: June 29, 2021Assignee: SiFive, Inc.Inventors: Yunsup Lee, Richard Xia, Derek Pappas, Mark Nugent, Henry Cook, Wesley Waylon Terpstra, Pin Hung Chen
-
Publication number: 20200042664Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.Type: ApplicationFiled: August 1, 2019Publication date: February 6, 2020Inventors: Yunsup Lee, Richard Xia, Derek Pappas, Mark Nugent, Henry Cook, Wesley Waylon Terpstra, Pin Hung Chen
-
Patent number: 9292265Abstract: Basic blocks within a thread program are characterized for convergence based on variance analysis or corresponding instructions. Each basic block is marked as divergent based on transitive control dependence on a block that is either divergent or comprising a variant branch condition. Convergent basic blocks that are defined by invariant instructions are advantageously identified as candidates for scalarization by a thread program compiler.Type: GrantFiled: May 9, 2012Date of Patent: March 22, 2016Assignee: NVIDIA CorporationInventors: Vinod Grover, Yunsup Lee, Xiangyun Kong, Gautam Chakrabarti, Ronny M. Krashinsky
-
Publication number: 20130305021Abstract: Basic blocks within a thread program are characterized for convergence based on variance analysis or corresponding instructions. Each basic block is marked as divergent based on transitive control dependence on a block that is either divergent or comprising a variant branch condition. Convergent basic blocks that are defined by invariant instructions are advantageously identified as candidates for scalarization by a thread program compiler.Type: ApplicationFiled: May 9, 2012Publication date: November 14, 2013Inventors: Vinod GROVER, Yunsup LEE, Xiangyun KONG, Gautam CHAKRABARTI, Ronny M. KRASHINSKY