Patents by Inventor Yunxiang DI

Yunxiang DI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11979136
    Abstract: A package structure of an air gap type semiconductor device includes a carrier; a semiconductor chip; and a bonding layer disposed between the carrier and the semiconductor chip. A first cavity is formed in the bonding layer and enclosed by the semiconductor chip and the carrier to at least aligned with a portion of an active region of the semiconductor chip. An encapsulation layer and the bonding layer are on a same side of the carrier to encapsulate the semiconductor chip and an exposed region of the bonding layer. At least one portion of the encapsulation layer is formed between the semiconductor chip and the carrier along a direction perpendicular to a lateral surface of the carrier. Interconnection structures formed on a side of the carrier different from a side with the bonding layer. Each interconnection structure is electrically connected to a corresponding input/output electrode of the semiconductor chip.
    Type: Grant
    Filed: May 19, 2023
    Date of Patent: May 7, 2024
    Assignee: Ningbo Semiconductor International Corporation
    Inventors: Yunxiang Di, Mengbin Liu, Situo Xu
  • Publication number: 20230291379
    Abstract: A package structure of an air gap type semiconductor device includes a carrier; a semiconductor chip; and a bonding layer disposed between the carrier and the semiconductor chip. A first cavity is formed in the bonding layer and enclosed by the semiconductor chip and the carrier to at least aligned with a portion of an active region of the semiconductor chip. An encapsulation layer and the bonding layer are on a same side of the carrier to encapsulate the semiconductor chip and an exposed region of the bonding layer. At least one portion of the encapsulation layer is formed between the semiconductor chip and the carrier along a direction perpendicular to a lateral surface of the carrier. Interconnection structures formed on a side of the carrier different from a side with the bonding layer. Each interconnection structure is electrically connected to a corresponding input/output electrode of the semiconductor chip.
    Type: Application
    Filed: May 19, 2023
    Publication date: September 14, 2023
    Inventors: Yunxiang DI, Mengbin LIU, Situo XU
  • Patent number: 11695387
    Abstract: The present disclosure provides a package structure of an air gap type semiconductor device and its fabrication method. The fabrication method includes forming a bonding layer having a first opening on a carrier; disposing a semiconductor chip on the bonding layer, thereby forming a first cavity at the first opening, where the first cavity is at least aligned with a portion of an active region of the semiconductor chip; performing an encapsulation process to encapsulate the semiconductor chip on the carrier; lastly, forming through holes passing through the carrier where each through hole is aligned with a corresponding input/output electrode region of the semiconductor chip, and forming interconnection structures on a side of the carrier different from a side with the bonding layer, where each interconnection structure passes through a corresponding through hole and is electrically connected to an corresponding input/output electrode.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: July 4, 2023
    Assignee: NINGBO SEMICONDUCTOR INTERNATIONAL CORPORATION (SHANGHAI BRANCH)
    Inventors: Yunxiang Di, Mengbin Liu, Situo Xu
  • Publication number: 20200366267
    Abstract: The present disclosure provides a package structure of an air gap type semiconductor device and its fabrication method. The fabrication method includes forming a bonding layer having a first opening on a carrier; disposing a semiconductor chip on the bonding layer, thereby forming a first cavity at the first opening, where the first cavity is at least aligned with a portion of an active region of the semiconductor chip; performing an encapsulation process to encapsulate the semiconductor chip on the carrier; lastly, forming through holes passing through the carrier where each through hole is aligned with a corresponding input/output electrode region of the semiconductor chip, and forming interconnection structures on a side of the carrier different from a side with the bonding layer, where each interconnection structure passes through a corresponding through hole and is electrically connected to an corresponding input/output electrode.
    Type: Application
    Filed: November 18, 2019
    Publication date: November 19, 2020
    Inventors: Yunxiang DI, Mengbin LIU, Situo XU