Patents by Inventor Yunyun XIAO

Yunyun XIAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Phase-aware DDR command dynamic scheduling
    Patent number: 11430496
    Abstract: A method for performing phase aware dynamic scheduling of a plurality of double data rate (DDR) commands includes determining a ratio of a frequency of DDR controller clock to a frequency of a DDR clock. The method includes determining a number of clock cycles of the DDR clock required for each DDR command of the plurality of DDR commands. The method includes, based on the ratio of the frequency of the DDR controller clock to the frequency of the DDR clock and the number of clock cycles of the DDR clock required for each DDR command, determining a sequence of the plurality of DDR commands according to a priority corresponding to the each DDR command, and transmitting the plurality of DDR commands to DDR devices over one or more clock cycles of the DDR controller clock according to the determined sequence of the plurality of DDR commands.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: August 30, 2022
    Assignee: SYNOPSYS, INC.
    Inventors: Jun Zhu, Yunyun Xiao
  • Phase-Aware DDR Command Dynamic Scheduling
    Publication number: 20210375341
    Abstract: A method for performing phase aware dynamic scheduling of a plurality of double data rate (DDR) commands includes determining a ratio of a frequency of DDR controller clock to a frequency of a DDR clock. The method includes determining a number of clock cycles of the DDR clock required for each DDR command of the plurality of DDR commands. The method includes, based on the ratio of the frequency of the DDR controller clock to the frequency of the DDR clock and the number of clock cycles of the DDR clock required for each DDR command, determining a sequence of the plurality of DDR commands according to a priority corresponding to the each DDR command, and transmitting the plurality of DDR commands to DDR devices over one or more clock cycles of the DDR controller clock according to the determined sequence of the plurality of DDR commands.
    Type: Application
    Filed: April 30, 2021
    Publication date: December 2, 2021
    Applicant: Synopsys, Inc.
    Inventors: Yunyun XIAO, Jun ZHU