Abstract: Disclosed are a method for manufacturing a carrier structure suitable for chiplet fine lines and a carrier structure. The method includes: preparing a temporary bonding layer on a temporary carrier, and preparing a pin interconnection layer on the temporary bonding layer, preparing at least one fine line interconnection layer on the pin interconnection layer; preparing a core layer on the at least one fine line interconnection layer with a second electrically conductive structure interconnected with the at least one fine line interconnection layer and/or the pin interconnection layer, preparing at least one build-up layer connected to the fine line interconnection layer on the core layer, and de-bonding the temporary bonding layer to obtain the carrier structure. The solutions can prepare fine lines on a carrier structure and ensure the yield of fine line interconnection lines, thus improving the manufacturability of the fine lines, carrier structure and packaging structure.

Abstract: A substrate bonding method includes: providing a first and a second substrate; forming, on the first substrate, a first metal micro-bump array including first metal pillar(s) formed on the first substrate and first metal nanowires formed thereon and spaced apart from each other; forming, on the second substrate, a second metal micro-bump array including second metal pillar(s) formed on the second substrate and second metal nanowires formed thereon and spaced apart from each other; pressing the first substrate onto the second substrate, such that the first and second metal micro-bump arrays are positioned and staggered with each other, forming a physically interwoven interlocking structure between the first and second metal nanowires; applying a filling material between the first and second substrates; curing the filling material to form a bonding cavity; and then performing confined heating reflux on the first and second metal micro-bump arrays in the bonding cavity.

Abstract: A chip stack packaging structure and method includes: a base chip layer, including a base chip with pins on the front surface; at least one stacked chip layer, which is formed on the base chip layer, has an inter-chip insulating layer and at least one stacked chip attached to the insulating layer and pins on the front surface, where the front surface of the stacked chip faces the front surface of the base chip; and a top insulating layer, stacked on the stacked chip layer farthest from the base chip layer. A vertical interconnection hole is formed inside the inter-chip insulating layer to allow the corresponding pins to be communicated vertically so as to be electrically connected. Inside the vertical interconnection hole, a conductive material layer is formed that makes the corresponding pins electrically connected; the stacked chip is thinned and reduced after being attached to the inter-chip insulating layer.

Abstract: A chip stack packaging structure and method includes: a base chip layer, including a base chip with pins on the front surface; at least one stacked chip layer, which is formed on the base chip layer, has an inter-chip insulating layer and at least one stacked chip attached to the insulating layer and pins on the front surface, where the front surface of the stacked chip faces the front surface of the base chip; and a top insulating layer, stacked on the stacked chip layer farthest from the base chip layer. A vertical interconnection hole is formed inside the inter-chip insulating layer to allow the corresponding pins to be communicated vertically so as to be electrically connected. Inside the vertical interconnection hole, a conductive material layer is formed that makes the corresponding pins electrically connected; the stacked chip is thinned and reduced after being attached to the inter-chip insulating layer.

Abstract: A chip packaging method and a chip packaging structure is disclosed. The method includes: attaching at least two chips to one side of substrate by adhesive layer, wherein device surface of the chip faces the substrate, and the substrate is provided therein with substrate wiring structure and/or chip; performing thinning treatment on the at least two chips provided on one side of the substrate, wherein the thinning treatment includes etching only the chips to reduce the thickness of the chips; plastically sealing the chips having undergone the thinning treatment to form a plastically sealed arrangement layer, and stacking at least two such plastically sealed arrangement layers on the substrate along plastic sealing direction; and punching the chips having undergone the thinning treatment to form first interconnection hole connecting the chips having undergone the thinning treatment to the substrate wiring structure, the chip in substrate, or the plastically sealed arrangement layer.

Abstract: Provided are a chip interconnection package structure and method, including: forming a sacrificial pattern layer on a support structure; forming an interconnection winding pattern layer on the sacrificial pattern layer, wherein the interconnection winding pattern layer is corresponding to a sacrificial pattern of the sacrificial pattern layer in position; forming a first insulating layer on the interconnection winding pattern layer; forming a plurality of chips arranged at intervals on the first insulating layer, wherein the plurality of chips are respectively corresponding to the interconnection winding pattern of the interconnection winding pattern layer in position; and removing the support structure, and forming, on one side of the sacrificial pattern layer, a first interconnection hole penetrating through the sacrificial pattern, the interconnection winding pattern and the first insulating layer, and making the first interconnection hole aligned and communicated with a first interconnection pin of the ch