Patents by Inventor Yuping Cui
Yuping Cui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11574103Abstract: Aspects of the invention provide means for addressing layout retargeting shortfalls. Initially, an original design shape in the layout is allowed to be simulated by process simulation to form process simulation contours. A polygon is then fitted to the process simulation contours to form a fitted simulated shape. Subsequently, whether the fitted simulated shape differs from the original design shape is detected. The process simulation may reflect the changes to the layout that occur at a foundry as part of a retargeting process. Advantageously, addressing a layout for retargeting shortfalls in accordance with aspects of the invention is likely to result in manufactured semiconductor devices having higher yields and reliability than those produced from a like layout that is not addressed in this manner.Type: GrantFiled: January 31, 2020Date of Patent: February 7, 2023Assignee: International Business Machines CorporationInventors: Dongbing Shao, Rasit Onur Topaloglu, Geng Han, Yuping Cui
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Publication number: 20210240899Abstract: Aspects of the invention provide means for addressing layout retargeting shortfalls. Initially, an original design shape in the layout is allowed to be simulated by process simulation to form process simulation contours. A polygon is then fitted to the process simulation contours to form a fitted simulated shape. Subsequently, whether the fitted simulated shape differs from the original design shape is detected. The process simulation may reflect the changes to the layout that occur at a foundry as part of a retargeting process. Advantageously, addressing a layout for retargeting shortfalls in accordance with aspects of the invention is likely to result in manufactured semiconductor devices having higher yields and reliability than those produced from a like layout that is not addressed in this manner.Type: ApplicationFiled: January 31, 2020Publication date: August 5, 2021Inventors: Dongbing Shao, Rasit Onur Topaloglu, Geng Han, Yuping Cui
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Publication number: 20170351799Abstract: Semiconductor layout generation includes: calculating, for a design rule constraint, a slack value for a subset of elements of a proposed semiconductor layout; generating a plurality of alternative layouts, where each of the alternative layouts includes a variation of interdependent characteristics of the subset of elements and a slack value for the subset of elements of each of the alternative layouts is less than the calculated slack value of subset of elements of the proposed layout; and calculating, by the layout design module for each of the alternative layouts, a risk value indicating the alternative layout's risk of fabrication failure.Type: ApplicationFiled: June 6, 2016Publication date: December 7, 2017Inventors: Atsushi Azuma, Yuping Cui, James A. Culp, Marco Facchini, Shaoning Yao
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Patent number: 9836570Abstract: Semiconductor layout generation includes: calculating, for a design rule constraint, a slack value for a subset of elements of a proposed semiconductor layout; generating a plurality of alternative layouts, where each of the alternative layouts includes a variation of interdependent characteristics of the subset of elements and a slack value for the subset of elements of each of the alternative layouts is less than the calculated slack value of subset of elements of the proposed layout; and calculating, by the layout design module for each of the alternative layouts, a risk value indicating the alternative layout's risk of fabrication failure.Type: GrantFiled: June 6, 2016Date of Patent: December 5, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Atsushi Azuma, Yuping Cui, James A. Culp, Marco Facchini, Shaoning Yao
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Patent number: 9590766Abstract: A multicarrier baseband peak elimination device and method are disclosed. The device includes: K branches, a peak selection module, an error signal generation module, and an adder; wherein K is an integer greater than 1; and each branch includes a delayer, a digital up conversion module, a first numerically controlled oscillator, a first multiplier, a second numerically controlled oscillator, a second multiplier, a digital down conversion module, an offset pulse generation module, and a subtractor.Type: GrantFiled: September 13, 2013Date of Patent: March 7, 2017Assignee: ZTE CorporationInventors: Feng Zeng, Weiming Pan, Dameng Ren, Yuping Cui
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Publication number: 20160261372Abstract: A multicarrier baseband peak elimination device and method are disclosed. The device includes: K branches, a peak selection module, an error signal generation module, and an adder; wherein K is an integer greater than 1; and each branch includes a delayer, a digital up conversion module, a first numerically controlled oscillator, a first multiplier, a second numerically controlled oscillator, a second multiplier, a digital down conversion module, an offset pulse generation module, and a subtractor.Type: ApplicationFiled: September 13, 2013Publication date: September 8, 2016Applicant: ZTE CORPORATIONInventors: Feng ZENG, Weiming PAN, Dameng; REN, Yuping CUI
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Patent number: 7350183Abstract: A method for performing model based optical proximity correction (MBOPC) and a system for performing MBOPC is described, wherein the process model is decomposed into a constant process model term and a pattern dependent portion. The desired wafer target is modified by the constant process model term to form a simulation target that is used as the new target within the MBOPC process. The pattern dependent portion of the model is used as the process model in the MBOPC algorithm. This results final mask designs that result in improved across-chip line width variations, and a more robust MBOPC process.Type: GrantFiled: November 5, 2004Date of Patent: March 25, 2008Assignee: International Business Machines CorporationInventors: Yuping Cui, Scott M. Mansfield
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Publication number: 20060101370Abstract: A method for performing model based optical proximity correction (MBOPC) and a system for performing MBOPC is described, wherein the process model is decomposed into a constant process model term and a pattern dependent portion. The desired wafer target is modified by the constant process model term to form a simulation target that is used as the new target within the MBOPC process. The pattern dependent portion of the model is used as the process model in the MBOPC algorithm. This results final mask designs that result in improved across-chip line width variations, and a more robust MBOPC process.Type: ApplicationFiled: November 5, 2004Publication date: May 11, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yuping Cui, Scott Mansfield
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Patent number: 7018746Abstract: A method of verifying the placement of sub-resolution assist features (SRAFs) in a photomask layout is described. SRAFs are added to the photomask layout to enhance the process window for semi-isolated and isolated features. Rules are provided to automatically place the SRAFs into the layout. When deficiencies are detected in the assist feature design or in the automated SRAF placement program, the placement of SRAFs requires verification. The method verifies the correct placement by defining a unique image property linked to the accurate placement of the assist features, and combines it with in-situ image simulation of the individual layout.Type: GrantFiled: April 15, 2003Date of Patent: March 28, 2006Assignee: International Business Machines CorporationInventors: Yuping Cui, Rama Nand Singh
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Publication number: 20040209169Abstract: A method of verifying the placement of sub-resolution assist features (SRAFs) in a photomask layout is described. SRAFs are added to the photomask layout to enhance the process window for semi-isolated and isolated features. Rules are provided to automatically place the SRAFs into the layout. When deficiencies are detected in the assist feature design or in the automated SRAF placement program, the placement of SRAFs requires verification. The method verifies the correct placement by defining a unique image property linked to the accurate placement of the assist features, and combines it with in-situ image simulation of the individual layout.Type: ApplicationFiled: April 15, 2003Publication date: October 21, 2004Applicant: International Business Machines CorporationInventors: Yuping Cui, Rama Nand Singh