Abstract: In a method for fabricating a semiconductor device, a stack of alternating insulating layers and sacrificial layers are formed over a substrate. A staircase having a plurality of steps are formed in the stack. Each of the steps has a tread and a riser and further includes a respective pair of the insulating layer and the sacrificial layer over the insulating layer of the respective step. A dielectric layer is formed along the treads and risers of the steps and is doped with one or a combination of carbon, phosphorous, boron, arsenic, and oxygen. The sacrificial layers are further replaced with a conductive material to form word line layers that are arranged between the insulating layers. A plurality of word line contacts are formed to extend from the word line layers of the plurality of steps, and further extend through the dielectric layer.

Abstract: Embodiments of wet processing systems and methods for uniform wet processing are disclosed. A method described in the present disclosure includes measuring one or more wafer characteristics of a wafer using a plurality of detectors and determining a wafer profile of the wafer based on the measured one or more wafer characteristics. The method also includes setting first and second sets of wet processing parameters of a wet processing system for respective first and second wafer regions based on the wafer profile, where a value of at least one wet processing parameter is different between the first and second sets of wet processing parameters. The method further includes performing wet processing on the wafer by dispensing one or more chemicals onto the first and second wafer regions according to the respective first and second sets of wet processing parameters.

Abstract: Examples of the present application disclose a semiconductor device and a fabrication method thereof and a memory system. The semiconductor device includes: a stack structure including first regions and second regions; channel structures that are located in the first regions and penetrate through the stack structure along a first direction; and gate line isolation structures that are located in the second regions and extend along a second direction, wherein the gate line isolation structures penetrate through the stack structure along the first direction and are in a concavo-convex shape along a third direction.

Abstract: A 3D memory device includes a conductor/insulator stack containing a conductive layer and a dielectric layer alternatingly stacked, a channel hole structure in the conductor/insulator stack, and a gate line slit (GLS) structure. The GLS structure includes a main section and an end section. The main section extends along a first direction and has a first width measured along a second direction that is perpendicular to the first direction. The end section has a second width measured along the second direction. The second width is larger than the first width.

Abstract: A 3D memory device includes a conductor/insulator stack, a region of memory cells in the conductor/insulator stack, and a gate line slit (GLS) structure extending along a direction. The GLS structure includes a first section, a second section, and a third section. The second section is between the first and third sections. The width of the second section is larger than the widths of the first and third sections.

Abstract: In a method for fabricating a semiconductor device, a stack of alternating insulating layers and sacrificial layers are formed over a substrate. A staircase having a plurality of steps are formed in the stack, where each of the plurality of steps has a tread and a riser and further includes a respective pair of the insulating layer and the sacrificial layer over the insulating layer of the respective step. A dielectric layer is formed along the treads and risers of the plurality of steps. The dielectric layer is doped with one or a combination of carbon, phosphorous, boron, arsenic, and oxygen. The sacrificial layers are further replaced with a conductive material to form word line layers that are arranged between the insulating layers. A plurality of word line contacts are formed to extend from the word line layers of the plurality of steps, and further extend through the dielectric layer.

Abstract: Embodiments of wet processing systems and methods for uniform wet processing are disclosed. A method described in the present disclosure includes measuring one or more wafer characteristics of a wafer using a plurality of detectors and determining a wafer profile of the wafer based on the measured one or more wafer characteristics. The method also includes setting first and second sets of wet processing parameters of a wet processing system for respective first and second wafer regions based on the wafer profile, where a value of at least one wet processing parameter is different between the first and second sets of wet processing parameters. The method further includes performing wet processing on the wafer by dispensing one or more chemicals onto the first and second wafer regions according to the respective first and second sets of wet processing parameters.

Abstract: Embodiments of wet processing systems and methods for uniform wet processing are disclosed. A method described in the present disclosure includes measuring one or more wafer characteristics of a wafer using a plurality of detectors and determining a wafer profile of the wafer based on the measured one or more wafer characteristics. The method also includes setting first and second sets of wet processing parameters of a wet processing system for respective first and second wafer regions based on the wafer profile, where a value of at least one wet processing parameter is different between the first and second sets of wet processing parameters. The method further includes performing wet processing on the wafer by dispensing one or more chemicals onto the first and second wafer regions according to the respective first and second sets of wet processing parameters.

Abstract: Methods of treating diseases in which plasma leakage and/or vascular permeability occurs, for example, inflammatory skin diseases, particularly psoriasis, with a vascular endothelial growth factor (VEGF) antagonist. Further included are methods for enhacing wound healing with a VEGF antagonist.

Abstract: Modified chimeric polypeptides with improved pharmacokinetics are disclosed. Specifically, modified chimeric Flt1 receptor polypeptides that have been modified in such a way as to improve their pharmacokinetic profile are disclosed. Also disclosed are methods of making and using the modified polypeptides including but not limited to using the modified polypeptides to decrease or inhibit plasma leakage and/or vascular permeability in a mammal. Also disclosed are methods of treating diseases in which plasma leakage and/or vascular permeability occurs, for example, inflammatory skin diseases.

Abstract: Modified chimeric polypeptides with improved pharmacokinetics are disclosed. Specifically, modified chimeric Fit1 receptor polypeptides that have been modified in such a way as to improve their pharmacokinetic profile are disclosed. Also disclosed are methods of making and using the modified polypeptides including but not limited to using the modified polypeptides to decrease or inhibit plasma leakage and/or vascular permeability in a mammal. Also disclosed are methods of treating diseases in which plasma leakage and/or vascular permeability occurs, for example, inflammatory skin diseases.