Patents by Inventor Yupu Zhang

Yupu Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11927713
    Abstract: A method, a device and a medium for acquiring logging parameters are provided, wherein the logging parameters include gas-bearing porosities, and the method includes: acquiring a two-dimensional nuclear magnetic logging analysis graph; determining a gas-bearing region from the two-dimensional nuclear magnetic logging analysis graph; and summing contour values of the gas-bearing region as a gas-bearing porosity. The device for acquiring logging parameters includes a processor and a computer readable storage medium, wherein instructions are stored in the computer readable storage medium, and the processor executes the instructions to perform the foregoing method for acquiring logging parameters. The medium for acquiring logging parameters stores computer executable instructions, which are used for executing the foregoing method for acquiring logging parameters.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: March 12, 2024
    Assignee: CHINA OILFIELD SERVICES LIMITED
    Inventors: Zhimin Jiang, Yupu Dang, Zhibo Xue, Jiawei Zhang
  • Patent number: 11144237
    Abstract: Systems and methods for concurrent reading and writing in shared, persistent byte-addressable non-volatile memory is described herein. One method includes in response to initiating a write sequence to one or more memory elements, checking an identifier memory element to determine whether a write sequence is in progress. In addition, the method includes updating an ingress counter. The method also includes adding process identification associated with a writer node to the identifier memory element. Next, a write operation is performed. After the write operation, an egress counter is incremented and the identifier memory element is reset to an expected value.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: October 12, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Milind M. Chabbi, Yupu Zhang, Haris Volos, Kimberly Keeton
  • Patent number: 10942824
    Abstract: Exemplary embodiments herein describe programming models and frameworks for providing parallel and resilient tasks. Tasks are created in accordance with predetermined structures. Defined tasks are stored as data objects in a shared pool of memory that is made up of disaggregated memory communicatively coupled via a high performance interconnect that supports atomic operations as descried herein. Heterogeneous compute nodes are configured to execute tasks stored in the shared memory. When compute nodes fail, they do not impact the shared memory, the tasks or other data stored in the shared memory, or the other non-failing compute nodes. The non-failing compute nodes can take on the responsibility of executing tasks owned by other compute nodes, including tasks of a compute node that fails, without needing a centralized manager or schedule to re-assign those tasks. Task processing can therefore be performed in parallel and without impact from node failures.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: March 9, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Haris Volos, Kimberly Keeton, Sharad Singhal, Yupu Zhang
  • Publication number: 20210034281
    Abstract: Systems and methods for concurrent reading and writing in shared, persistent byte-addressable non-volatile memory is described herein. One method includes in response to initiating a write sequence to one or more memory elements, checking an identifier memory element to determine whether a write sequence is in progress. In addition, the method includes updating an ingress counter. The method also includes adding process identification associated with a writer node to the identifier memory element. Next, a write operation is performed. After the write operation, an egress counter is incremented and the identifier memory element is reset to an expected value.
    Type: Application
    Filed: August 1, 2019
    Publication date: February 4, 2021
    Inventors: Milind M. Chabbi, Yupu Zhang, Haris Volos, Kimberly Keeton
  • Patent number: 10705951
    Abstract: An example system comprises one or more processing nodes to execute one or more processes; a switching fabric coupled to the one or more processing nodes; a fabric-attached memory (FAM) coupled with the switching fabric; and a memory allocator to allocate and release memory in the FAM in response to memory allocation requests and memory release requests from the one or more processes. The memory allocator is to partition the FAM into a memory shelf comprising a plurality of memory books of equal size. The memory allocator is to map a shelf into a virtual memory zone, the zone aligned with the boundaries of one or more books. The memory allocator is to maintain an indexed free-memory list where each index level is an entry point to a list of free memory blocks of a particular size in the zone, and the memory allocator to maintain a bitmap of the zone to identify if a memory block of a particular size is allocated.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: July 7, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Yuvraj Patel, Yupu Zhang, Daniel Gmach
  • Publication number: 20200110676
    Abstract: Exemplary embodiments herein describe programming models and frameworks for providing parallel and resilient tasks. Tasks are created in accordance with predetermined structures. Defined tasks are stored as data objects in a shared pool of memory that is made up of disaggregated memory communicatively coupled via a high performance interconnect that supports atomic operations as descried herein. Heterogeneous compute nodes are configured to execute tasks stored in the shared memory. When compute nodes fail, they do not impact the shared memory, the tasks or other data stored in the shared memory, or the other non-failing compute nodes. The non-failing compute nodes can take on the responsibility of executing tasks owned by other compute nodes, including tasks of a compute node that fails, without needing a centralized manager or schedule to re-assign those tasks. Task processing can therefore be performed in parallel and without impact from node failures.
    Type: Application
    Filed: October 8, 2018
    Publication date: April 9, 2020
    Inventors: Haris Volos, Kimberly Keeton, Sharad Singhal, Yupu Zhang
  • Patent number: 10489310
    Abstract: Determining cache value currency using persistent markers is disclosed herein. In one example, a cache entry is retrieved from a local cache memory device. The cache entry includes a key, a value to be used by the computing device, and a marker flag to determine whether the cache entry is current. The local cache memory device also includes a marker location that indicates a location of a marker in a shared persistent fabric-attached memory (FAM). Using a marker location, the marker is retrieved from the shared persistent FAM. From the marker and the marker flag, it is determined whether the cache entry is current. The shared FAM pool is connected to the local cache memory devices of multiple computing devices.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: November 26, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Kimberly Keeton, Yupu Zhang, Haris Volos, Ram Swaminathan, Evan R. Kirshenbaum
  • Publication number: 20190236001
    Abstract: An example system comprises one or more processing nodes to execute one or more processes; a switching fabric coupled to the one or more processing nodes; a fabric-attached memory (FAM) coupled with the switching fabric; and a memory allocator to allocate and release memory in the FAM in response to memory allocation requests and memory release requests from the one or more processes. The memory allocator is to partition the FAM into a memory shelf comprising a plurality of memory books of equal size. The memory allocator is to map a shelf into a virtual memory zone, the zone aligned with the boundaries of one or more books. The memory allocator is to maintain an indexed free-memory list where each index level is an entry point to a list of free memory blocks of a particular size in the zone, and the memory allocator to maintain a bitmap of the zone to identify if a memory block of a particular size is allocated.
    Type: Application
    Filed: January 31, 2018
    Publication date: August 1, 2019
    Inventors: Yuvraj PATEL, Yupu ZHANG, Daniel GMACH
  • Publication number: 20190121750
    Abstract: Determining cache value currency using persistent markers is disclosed herein. In one example, a cache entry is retrieved from a local cache memory device. The cache entry includes a key, a value to be used by the computing device, and a marker flag to determine whether the cache entry is current. The local cache memory device also includes a marker location that indicates a location of a marker in a shared persistent fabric-attached memory (FAM). Using a marker location, the marker is retrieved from the shared persistent FAM. From the marker and the marker flag, it is determined whether the cache entry is current. The shared FAM pool is connected to the local cache memory devices of multiple computing devices.
    Type: Application
    Filed: October 20, 2017
    Publication date: April 25, 2019
    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Kimberly Keeton, Yupu Zhang, Haris Volos, Ram Swaminathan, Evan R. Kirshenbaum