Abstract: An integrated circuit with toggle suppression logic for built-in self-test is provided. The integrated includes a loading circuit configured to operate in a shift mode based on a first enable signal and a capture mode based on a second enable signal. The integrated circuit includes a switching element configured to receive the first enable signal and the second enable signal to generate a third enable signal. The integrated circuit includes combinational logic coupled to the loading circuit and the switching element, in which the combinational logic is configured to receive the third enable signal. The third enable signal is configured to disable toggling in the combinational logic while the loading circuit operates in the shift mode.

Abstract: An integrated circuit with toggle suppression logic for built-in self-test is provided. The integrated includes a loading circuit configured to operate in a shift mode based on a first enable signal and a capture mode based on a second enable signal. The integrated circuit includes a switching element configured to receive the first enable signal and the second enable signal to generate a third enable signal. The integrated circuit includes combinational logic coupled to the loading circuit and the switching element, in which the combinational logic is configured to receive the third enable signal. The third enable signal is configured to disable toggling in the combinational logic while the loading circuit operates in the shift mode.

Abstract: An integrated circuit with low-power built-in self-test logic (“IC-LPBIST”) is disclosed. The IC-LPBIST may include combinational logic and a loading circuit enabled to load a shift test pattern of data into the loading circuit without powering the combinational logic of the IC-LPBIST, wherein the shift test pattern of data is configured to test the combinational logic for logical faults.

Abstract: Timing vectors are used to pass execution of time-dependent operations from firmware/software to a hardware component (e.g., a state machine). These vectors may be stored as a vector table in a data memory that is accessible by both the firmware/software and the hardware component. Based on the processing being performed in the system, the firmware/software will determine that one or more operations are to be performed at a certain time. The firmware/software stores a reference to that time and the operation(s) in a vector. The hardware component monitors time in the system and the vectors to determine whether the current time matches the time associated with a given vector. When there is a match, the hardware component causes the operation(s) associated with the vector to be performed. The system also may perform different operations at a given time depending on the operating condition (e.g., state) of the system.

Abstract: In one general aspect, a system may include a circuit board, a first integrated circuit attached to the circuit board, and a second integrated circuit attached to the circuit board being separate from the first integrated circuit and configured to operate in multiple power domains that include at least a core power domain and an I/O power domain and that is configured with a logic gate to receive and process external requests from the first integrated circuit and internal requests from the second integrated circuit for a common external resource.

Abstract: In one general aspect, a system may include a circuit board, a first integrated circuit attached to the circuit board, and a second integrated circuit attached to the circuit board being separate from the first integrated circuit and configured to operate in multiple power domains that include at least a core power domain and an I/O power domain and that is configured with a logic gate to receive and process external requests from the first integrated circuit and internal requests from the second integrated circuit for a common external resource.

Abstract: A host-side wireless interface services communications between a wireless user input device and a serviced host. The host-side wireless interface includes a wireless network interface, a host interface, and may include additional components. The wireless network interface wirelessly communicates with the wireless user input device. The host interface communicatively couples to the wireless interface and to the serviced host. When the serviced host initiates bootstrap operations via a Basic Input/Output System (BIOS), the host interface operates in a BIOS host interface mode to allow input from the wireless user input device to the BIOS during the bootstrap operations. Further, when the serviced host initiates Operating System (OS) operations, the host interface operates in an OS host interface mode, wherein the OS host interface mode differs from the BIOS host interface mode.

Abstract: A host-side wireless interface services communications between a wireless user input device and a serviced host. The host-side wireless interface includes a wireless network interface, a host-side wireless interface, and may include additional components. The wireless network interface wirelessly communicates with the wireless user input device. The wireless user input device and the serviced host computer interact to setup the operation of the wireless user input device with the serviced host computer without requiring input from another user input device. In setting up the wireless user input device, the host-side wireless interface storing configuration information in non-volatile memory.

Abstract: An embedded processor system including at least one gated power unit including an internal ROM and a power controller that provides one or more gated power signals to selectively provide power to each gated power unit. The power controller provides a gated clock signal to the embedded processor to selectively control power consumption of the processor. The power controller powers down each gated power unit after freezing the processor and then powers up each gated power unit before reactivating the processor. The embedded processor system may include isolation circuitry, such as clamp circuitry or the like, that is operative to minimize current flow into each gated power unit when powered down. The gated power units may include a static function. The ROM of an embedded ROM-based microprocessor system is powered down when the microprocessor is idle to reduce or otherwise eliminate intrinsic leakage.

Abstract: A host-side wireless interface services communications between a wireless user input device and a serviced host. The host-side wireless interface includes a wireless network interface, a host interface, and may include additional components. The wireless network interface wirelessly communicates with the wireless user input device. The host interface communicatively couples to the wireless interface and to the serviced host. When the serviced host initiates bootstrap operations via a Basic Input/Output System (BIOS), the host interface operates in a BIOS host interface mode to allow input from the wireless user input device to the BIOS during the bootstrap operations. Further, when the serviced host initiates Operating System (OS) operations, the host interface operates in an OS host interface mode, wherein the OS host interface mode differs from the BIOS host interface mode.

Abstract: An embedded ROM-based processor system including a processor, system memory, a programmable memory, a data selector and a patch controller. The system memory includes a read-only memory (ROM). The programmable memory stores patch information including patch code and one or more patch vectors. Each patch vector includes a break-out address from the ROM and a patch-in address to a corresponding location within the patch code. The data selector has an input coupled to the system memory and an output coupled to the processor. The patch controller is operative to compare an address provided by the processor with each break-out address to determine a breakout condition, and to control the selector to transfer the processor to a corresponding location within the patch code in response to a break-out condition. The programmable memory may be volatile memory, where the patch information is loaded from an external memory during initialization.

Abstract: A host-side wireless interface services communications between a wireless user input device and a serviced host. The host-side wireless interface includes a wireless network interface, a host interface, and may include additional components. The wireless network interface wirelessly communicates with the wireless user input device. The host interface communicatively couples to the wireless interface and to the serviced host. When the serviced host initiates bootstrap operations via a Basic Input/Output System (BIOS), the host interface operates in a BIOS host interface mode to allow input from the wireless user input device to the BIOS during the bootstrap operations. Further, when the serviced host initiates Operating System (OS) operations, the host interface operates in an OS host interface mode, wherein the OS host interface mode differs from the BIOS host interface mode.

Abstract: An embedded ROM-based processor system including a processor, system memory, a programmable memory, a data selector and a patch controller. The system memory includes a read-only memory (ROM). The programmable memory stores patch information including patch code and one or more patch vectors. Each patch vector includes a break-out address from the ROM and a patch-in address to a corresponding location within the patch code. The data selector has an input coupled to the system memory and an output coupled to the processor. The patch controller is operative to compare an address provided by the processor with each break-out address to determine a breakout condition, and to control the selector to transfer the processor to a corresponding location within the patch code in response to a break-out condition. The programmable memory may be volatile memory, where the patch information is loaded from an external memory during initialization.

Abstract: A host-side wireless interface services communications between a wireless user input device and a serviced host. The host-side wireless interface includes a wireless network interface, a host-side wireless interface, and may include additional components. The wireless network interface wirelessly communicates with the wireless user input device. The wireless user input device and the serviced host computer interact to setup the operation of the wireless user input device with the serviced host computer without requiring input from another user input device. In setting up the wireless user input device, the host-side wireless interface storing configuration information in non-volatile memory.

Abstract: An embedded processor system including at least one gated power unit including an internal ROM and a power controller that provides one or more gated power signals to selectively provide power to each gated power unit. The power controller provides a gated clock signal to the embedded processor to selectively control power consumption of the processor. The power controller powers down each gated power unit after freezing the processor and then powers up each gated power unit before re-activate the processor. The embedded processor system may include isolation circuitry, such as clamp circuitry or the like, that is operative to minimize current flow into each gated power unit when powered down. The gated power units may include a static function. The ROM of an embedded ROM-based microprocessor system is powered down when the microprocessor is idle to reduce or otherwise eliminate intrinsic leakage.