Abstract: A Buck constant voltage driver and an application circuit thereof, are disclosed. In the Buck constant voltage driver, the peripheral structure is remained unchanged for possessing the advantages of low cost and simplicity of the prior art. Meanwhile, in order to compensate the difference of output voltage caused by the change of the forward voltage drop under different output currents, an output voltage compensation module is added to the Buck constant voltage driver. The output voltage compensation module is operable to acquire an output current information based on the sampling voltage on the sampling resistor, and to compensate the preset first reference voltage according to the output current information, thus maintaining the output voltage of the Buck constant voltage driver constant, under different output current conditions.

Abstract: Disclosed by present disclosure are a Darlington transistor drive circuit, a Darlington transistor drive method and a switching power supply management chip. In this embodiment, the Darlington transistor is driven sectionally. At the beginning of the switching-on cycle, the driving of the primary transistor is not started temporarily, instead the drive source is used to drive the secondary transistor. After the secondary transistor is completely switched on, the drive source of the secondary transistor is switched off and the drive source of the primary transistor is switched on to drive the Darlington transistor. The primary and secondary transistor have been completely switched on, and the drive current of the secondary transistor never depend on the primary transistor, so the voltage at the input terminal of the secondary transistor can be smaller than the voltage at the control terminal of the secondary transistor. Such that the switching-on power loss is reduced.

Abstract: Disclosed is a power supply drive circuit, chip and method. In each switching-on cycle, the charging demand is considered. If the current switching-on cycle requires charging, after the drive tube is completely switched on in the current switching-on cycle, the sampling switch tube is switched off and the charging switch tube is switched on for using a small current which flows through the drive tube in the early stage of the switching-on cycle for charging. In the later stage of the current switching-on cycle, the sampling switch tube is switched on and the charging switch tube is switched off, such that the current outputted by the drive tube flows through the current sampling switch tube according to the normal path. In this way, the power supply voltage never changes with the output power, the cumbersome design and debugging of the power supply circuit are avoid.

Abstract: Disclosed is a soft-start circuit for power-up, which includes a reference value generation circuit, a protection threshold generation circuit and a control circuit. The reference value generation circuit outputs a reference value, which increases slowly, during a start-up process for power-up. The protection threshold generation circuit outputs a protection threshold, which increases slowly, during the start-up process for power-up. The control circuit controls an output voltage to increase slowly along with the reference value based on the reference value, during the start-up process for power-up, and to limit an output current based on the protection threshold to limit the output voltage, during the start-up process for power-up. In this way, even if the output current must operate at the peak current, a smoother current output is realized, and operation at the maximum peak current for a long-time during start-up is not allowed.

Abstract: A chip, a self-calibration circuit and method for chip parameter offset upon power-up are disclosed. The circuit includes a counting circuit, a calibration data latch circuit, a calibration data selection circuit and a parameter calibration circuit. The counting circuit outputs a sequentially scanned counting signal when receiving a valid enabling signal. The calibration data latch circuit latches the counting signal when receiving a valid latch signal. The calibration data selection circuit selects the counting signal latched by the calibration data latch circuit as a calibration signal when receiving the valid latch signal, otherwise selects the counting signal currently outputted as the calibration signal. The parameter calibration circuit implements a parameter calibration based on the calibration signal in a calibration mode, while outputs the valid latch signal when the parameter calibration satisfies a preset requirement.

Abstract: An adding circuit for multi-channel signals and an implementation method thereof are disclosed. The adding circuit for multi-channel signals includes an operational amplifier, a plurality of charge and discharge circuits, a charge transfer circuit, a switch sequence and a control circuit. In this disclosure, the duty cycle of each charge and discharge circuit and the charge transfer circuit can be programmed and preset according to the actual needs, which is not only suitable for the static voltage adding circuit, but also suitable for the dynamic voltage adding circuit. When there are multi-channel signals, the output interference caused by individual signals can be prevented. The area of the adding circuit can be greatly reduced. The adding circuit can be IP-based, controlled by programing and presetting a variety of combined adding algorithms, so the chip cost can be saved and a wide applicability in detection and monitoring can be provided.

Abstract: A Buck constant voltage driver and an application circuit thereof, are disclosed. In the Buck constant voltage driver, the peripheral structure is remained unchanged for possessing the advantages of low cost and simplicity of the prior art. Meanwhile, in order to compensate the difference of output voltage caused by the change of the forward voltage drop under different output currents, an output voltage compensation module is added to the Buck constant voltage driver. The output voltage compensation module is operable to acquire an output current information based on the sampling voltage on the sampling resistor, and to compensate the preset first reference voltage according to the output current information, thus maintaining the output voltage of the Buck constant voltage driver constant, under different output current conditions.

Abstract: A chip, a self-calibration circuit and method for chip parameter offset upon power-up are disclosed. The circuit includes a counting circuit, a calibration data latch circuit, a calibration data selection circuit and a parameter calibration circuit. The counting circuit outputs a sequentially scanned counting signal when receiving a valid enabling signal. The calibration data latch circuit latches the counting signal when receiving a valid latch signal. The calibration data selection circuit selects the counting signal latched by the calibration data latch circuit as a calibration signal when receiving the valid latch signal, otherwise selects the counting signal currently outputted as the calibration signal. The parameter calibration circuit implements a parameter calibration based on the calibration signal in a calibration mode, while outputs the valid latch signal when the parameter calibration satisfies a preset requirement.

Abstract: Disclosed are a Darlington transistor drive circuit, a Darlington transistor drive method implemented based on such Darlington transistor drive circuit, and a constant current switching power supply including such Darlington transistor drive circuit. The Darlington transistor drive circuit includes a drive current circuit, two switch units, and a drive control circuit used for controlling the two switch units to be switched off during the switching-on cycle of the Darlington transistor and to be switched on during a switching-off cycle of the Darlington transistor, and for changing an equivalent resistance of the two switch units at different stages during the switching- off cycle of the Darlington transistor. The switching-off time delay of the Darlington transistor is greatly reduced while achieving the EMI optimization. In additional, the switch loss of Darlington transistor is small when it is switched off, and the efficiency is improved.

Abstract: Disclosed are a Darlington transistor drive circuit, a Darlington transistor drive method implemented based on such Darlington transistor drive circuit, and a constant current switching power supply comprising such Darlington transistor drive circuit. The Darlington transistor drive circuit comprises a drive current circuit, two switch units, and a drive control circuit used for controlling the two switch units to be switched off during the switching-on cycle of the Darlington transistor and to be switched on during a switching-off cycle of the Darlington transistor, and for changing an equivalent resistance of the two switch units at different stages during the switching-off cycle of the Darlington transistor. The switching-off time delay of the Darlington transistor is greatly reduced while achieving the EMI optimization. In additional, the switch loss of Darlington transistor is small when it is switched off, and the efficiency is improved.

Abstract: A switching mode power supply, and a primary-side controlled PFM converter using the primary-side regulated PFM controller are discussed. In present embodiment, the primary side cycle by cycle switch peak current is no longer a constant. The time detector is added to monitor the waveform of primary-side sample voltage and then generate the duty cycle. The transfer function should be selected to satisfy a specific relationship of switching frequency and switch peak current against with output loading current. The new design shows higher switching frequency but lower value of switch peak current at light load condition. This resolves the audible noise and poor transient response issue from the prior art PFM controller.

Abstract: A switching mode power supply, and a primary-side controlled PFM converter using the primary-side regulated PFM controller are discussed. In present embodiment, the primary side cycle by cycle switch peak current is no longer a constant. The time detector is added to monitor the waveform of primary-side sample voltage and then generate the duty cycle. The transfer function should be selected to satisfy a specific relationship of switching frequency and switch peak current against with output loading current. The new design shows higher switching frequency but lower value of switch peak current at light load condition. This resolves the audible noise and poor transient response issue from the prior art PFM controller.