Patents by Inventor Yu-Ren Wang
Yu-Ren Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240175810Abstract: A gas sensing device for detecting a to-be-detected substance in a respiratory gas exhaled by a user includes a housing permitting entrance of the respiratory gas, and a sensing module disposed in the housing. The sensing module includes a light chamber permitting the respiratory gas to pass therethrough, a light source unit emitting light into the light chamber, first and second light sensing units outputting respectively first and second detected signals indicating first and second detected intensities respectively of first and second portions of the light whose wavelengths fall within first and second wavelength ranges, respectively, and a processing unit electrically connected to the first and second light sensing units and determining, based on the first and second detected signals, that the to-be-detected substance exists in the respiratory gas when a difference occurs in each of the first and second detected intensities over time.Type: ApplicationFiled: May 17, 2023Publication date: May 30, 2024Inventors: Yu-Ren HUANG, Li-Yu WANG, Ming-Chun HSIAO, Chun-Han HUANG, Yu-Da CHIU
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Publication number: 20240145597Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a first dielectric layer and a second dielectric layer successively over the source/drain regions; performing a first etching process to form an opening in the first dielectric layer and in the second dielectric layer, where the opening exposes an underlying electrically conductive feature; after performing the first etching process, performing a second etching process to enlarge a lower portion of the opening proximate to the substrate; and forming a contact plug in the opening after the second etching process.Type: ApplicationFiled: January 2, 2024Publication date: May 2, 2024Inventors: Yu-Lien Huang, Guan-Ren Wang, Ching-Feng Fu, Yun-Min Chang
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Patent number: 11974371Abstract: A light-emitting diode LED driver and a LED driving device including the LED driver are provided. The light-emitting diode LED driver includes a decoding circuit that receives a data signal and decodes the data signal to generate display data used to drive LEDs to emit light and display and a recovered clock signal. Further provided is an encoding circuit that encodes the decoded display data by using the recovered clock signal to generate an encoded data signal, where the data signal is encoded in a first encoding format, and the encoded data signal is encoded in a second encoding format.Type: GrantFiled: July 29, 2021Date of Patent: April 30, 2024Assignee: NOVATEK MICROELECTRONICS CORP.Inventors: Yu-Hsiang Wang, Che-Wei Yeh, Keko-Chun Liang, Yong-Ren Fang, Yi-Chuan Liu
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Patent number: 11961939Abstract: A method of manufacturing a light-emitting device, including: providing a substrate structure including a top surface; forming a precursor layer on the top surface; removing a portion of the precursor layer and a portion of the substrate from the top surface to form a base portion and a plurality of protrusions regularly arranged on the base portion; forming a buffer layer on the base portion and the plurality protrusions; and forming a III-V compound cap layer on the buffer layer; wherein one of the plurality of protrusions comprises a first portion and a second portion formed on the first portion; wherein the first portion is integrated with the base portion and has a first material which is the same as that of the base portion; and wherein the buffer layer contacts side surfaces of the plurality of protrusions and a surface of the base portion.Type: GrantFiled: June 23, 2022Date of Patent: April 16, 2024Assignee: EPISTAR CORPORATIONInventors: Peng Ren Chen, Yu-Shan Chiu, Wen-Hsiang Lin, Shih-Wei Wang, Chen Ou
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Patent number: 11955519Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.Type: GrantFiled: April 17, 2023Date of Patent: April 9, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
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Patent number: 11935920Abstract: In an embodiment, a device includes: a first source/drain region; a second source/drain region; an inter-layer dielectric (ILD) layer over the first source/drain region and the second source/drain region; a first source/drain contact extending through the ILD layer, the first source/drain contact connected to the first source/drain region; a second source/drain contact extending through the ILD layer, the second source/drain contact connected to the second source/drain region; and an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature including a dielectric liner and a void, the dielectric liner surrounding the void.Type: GrantFiled: July 27, 2022Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Lien Huang, Guan-Ren Wang, Ching-Feng Fu
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Publication number: 20240087960Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.Type: ApplicationFiled: November 13, 2023Publication date: March 14, 2024Inventors: Yu-Lien HUANG, Ching-Feng FU, Huan-Just LIN, Fu-Sheng LI, Tsai-Jung HO, Bor Chiuan HSIEH, Guan-Xuan CHEN, Guan-Ren WANG
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Patent number: 11916147Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a first dielectric layer and a second dielectric layer successively over the source/drain regions; performing a first etching process to form an opening in the first dielectric layer and in the second dielectric layer, where the opening exposes an underlying electrically conductive feature; after performing the first etching process, performing a second etching process to enlarge a lower portion of the opening proximate to the substrate; and forming a contact plug in the opening after the second etching process.Type: GrantFiled: June 29, 2022Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Yu-Lien Huang, Guan-Ren Wang, Ching-Feng Fu, Yun-Min Chang
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Publication number: 20240038844Abstract: A method for fabricating a high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a gate electrode on the p-type semiconductor layer, and then forming a source electrode and a drain electrode adjacent to two sides of the gate electrode. Preferably, the buffer layer further includes a bottom portion having a first carbon concentration and a top portion having a second carbon concentration, in which the second carbon concentration is less than the first carbon concentration and a thickness of the bottom portion is less than a thickness of the top portion.Type: ApplicationFiled: August 26, 2022Publication date: February 1, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Liang Kuo, Yen-Hsing Chen, Yen-Lun Chen, Ruei-Hong Shen, Tsung-Mu Yang, Yu-Ren Wang
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Patent number: 11876122Abstract: A method of forming a semiconductor device. A substrate having a fin structure is provided. A dummy gate is formed on the fin structure. A polymer block is formed adjacent to a corner between the dummy gate and the fin structure. The polymer block is subjected to a nitrogen plasma treatment, thereby forming a nitridation layer in proximity to a sidewall of the dummy gate under the polymer block. After subjecting the polymer block to the nitrogen plasma treatment, a seal layer is formed on the sidewall of the dummy gate and on the polymer block. An epitaxial layer is then grown on a source/drain region of the fin structure. The dummy gate is then replaced with a metal gate.Type: GrantFiled: November 27, 2022Date of Patent: January 16, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Wei Chang, Chia-Ming Kuo, Po-Jen Chuang, Fu-Jung Chuang, Shao-Wei Wang, Yu-Ren Wang, Chia-Yuan Chang
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Publication number: 20230386939Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the first fin-shaped structure into a first portion and a second portion, and more than two gate structures on the SDB structure. Preferably, the more than two gate structures include a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure disposed on the SDB structure.Type: ApplicationFiled: August 14, 2023Publication date: November 30, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
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Publication number: 20230352587Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure and an epitaxial structure. The gate structure is disposed on the substrate, and the epitaxial structure is disposed in the substrate, at one side of the gate structure. The epitaxial structure includes a portion being protruded from a top surface of the substrate, and the portion includes a discontinuous sidewall, with a distance between a turning point of the discontinuous sidewalls and the gate structure being a greatest distance between the epitaxial structure and the gate structure.Type: ApplicationFiled: July 4, 2023Publication date: November 2, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuang-Hsiu Chen, Sung-Yuan Tsai, Chi-Hsuan Tang, Chun-Wei Yu, Yu-Ren Wang
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Patent number: 11791219Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.Type: GrantFiled: November 7, 2022Date of Patent: October 17, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
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Patent number: 11791413Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, a gate structure extending on the fin in a second direction, and a seal layer located on the sidewall of the gate structure. A first peak carbon concentration is disposed in the seal layer. A first spacer layer is located on the seal layer. A second peak carbon concentration is disposed in the first spacer layer. A second spacer layer is located on the first spacer layer.Type: GrantFiled: August 2, 2021Date of Patent: October 17, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shi-You Liu, Shih-Cheng Chen, Chia-Wei Chang, Chia-Ming Kuo, Tsai-Yu Wen, Yu-Ren Wang
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Publication number: 20230268397Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.Type: ApplicationFiled: April 17, 2023Publication date: August 24, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
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Patent number: 11735661Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure and an epitaxial structure. The gate structure is disposed on the substrate, and the epitaxial structure is disposed in the substrate, at one side of the gate structure. The epitaxial structure includes a portion being protruded from a top surface of the substrate, and the portion includes a discontinuous sidewall, with a distance between a turning point of the discontinuous sidewalls and the gate structure being a greatest distance between the epitaxial structure and the gate structure.Type: GrantFiled: May 26, 2021Date of Patent: August 22, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuang-Hsiu Chen, Sung-Yuan Tsai, Chi-Hsuan Tang, Chun-Wei Yu, Yu-Ren Wang
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Publication number: 20230253457Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.Type: ApplicationFiled: April 17, 2023Publication date: August 10, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
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Patent number: 11695067Abstract: A high-electron mobility transistor includes a substrate; a channel layer on the substrate; a AlGaN layer on the channel layer; and a P—GaN gate on the AlGaN layer. The AlGaN layer comprises a first region and a second region. The first region has a composition that is different from that of the second region.Type: GrantFiled: September 21, 2022Date of Patent: July 4, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yen-Hsing Chen, Yu-Ming Hsu, Tsung-Mu Yang, Yu-Ren Wang
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Publication number: 20230207643Abstract: A high electron mobility transistor (HEMT) includes a substrate, a P-type III-V composition layer, a gate electrode and a carbon containing layer. The P-type III-V composition layer is disposed on the substrate, and the gate electrode is disposed on the P-type III-V composition layer. The carbon containing layer is disposed under the P-type III-V composition layer and includes a sunken surface, so as to function like an out diffusion barrier for preventing from the dopant within the P-type III-V composition layer diffusing into the stacked layers underneath during the annealing process.Type: ApplicationFiled: February 23, 2023Publication date: June 29, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Tsung-Mu Yang, Yu-Ren Wang
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Patent number: 11664426Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.Type: GrantFiled: March 3, 2022Date of Patent: May 30, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang