Patents by Inventor Yuri A. Vlasov

Yuri A. Vlasov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8426921
    Abstract: Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a substrate; a digital CMOS circuitry layer adjacent to the substrate; and a first bonding oxide layer adjacent to a side of the digital CMOS circuitry layer opposite the substrate. The top device layer comprises an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer having a buried oxide (BOX) with a thickness of greater than or equal to about 0.5 micrometers; and a second bonding oxide layer adjacent to the analog CMOS and photonics circuitry layer. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: April 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Solomon Assefa, Kuan-Neng Chen, Steven J. Koester, Yuri A. Vlasov
  • Patent number: 8129811
    Abstract: Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a digital CMOS circuitry layer; and a first bonding oxide layer adjacent to the digital CMOS circuitry layer. The top device layer comprises a substrate; an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer adjacent to the substrate, the SOI layer having a buried oxide (BOX) with a thickness of greater than or equal to about one micrometer; and a second bonding oxide layer adjacent to a side of the analog CMOS and photonics circuitry layer opposite the substrate. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.
    Type: Grant
    Filed: April 16, 2011
    Date of Patent: March 6, 2012
    Assignee: International Business Machines Corporation
    Inventors: Solomon Assefa, Kuan-Neng Chen, Steven J. Koester, Yuri A. Vlasov