Abstract: A high-speed sense amplifier includes a pair of cross-coupled inverters coupled to intermediate nodes and then to differential inputs nodes by a control circuit. The intermediate nodes are coupled together by a accelerator transistor that forms a current path when the sense amplifier is placed in a sensing state to provide parallel discharge paths for one or the other of output nodes. During precharge, the accelerator transistor operates to equalize the intermediate nodes to ready them for the next sense phase.

Abstract: A clocked CMOS sense amplifier for high speed latching of low voltage complementary signals. The present invention includes a sense amplifier having a controlled cross-coupled transistor structure, a control circuit, a current source, a recovery transistor and protective transistors. A CORE circuit is provided which may be used to form different logic structures. Two large n-channel transistors in a discharging chain are used in combination with the small capacitances of the cross-coupled nodes to provide maximum speed and high output.

Abstract: A multiport register file memory includes a cross-coupled sense amplifier as a storage element. A buffered switching circuit provides a voltage potential to the storage element in response to a write enable signal for switching-on/off the storage element. Each storage element provides two storage nodes which are coupled to corresponding switched bit lines. Coupling between each storage node and corresponding switched bit lines is provided by a pass transistor that is controlled by a word line attached to a gate of the pass transistor. The write operation begins by powering-off at least one controlled supply voltage rail that provides a voltage potential to the storage element. A small voltage swing of between two hundred and five hundred millivolts (200-500 mV) is supplied from the bit lines to the storage nodes of the sense amplifier through the pass transistors.

Abstract: A self-clocking sense amplifier includes first and second input nodes and first and second output nodes. A first N-Channel transistor has its drain connected to the first output node and its gate connected to the second output node. A second N-Channel transistor has its drain connected to the second output node and its gate connected to the first output node. An N-Channel pulldown transistor has its source connected to a first supply voltage potential, a drain connected to the drain of the first and second N-Channel transistors, and a gate connected to a pulldown node. A first P-Channel transistor has a source connected to the first input node, a drain connected to the first output node, and a gate connected to the second output node. A second P-Channel transistor has a source connected to the second input node, a drain connected to the second output node, and a gate connected to the first output node.