Abstract: A branch prediction mechanism 16, 18 within a multithreaded processor having hardware scheduling logic 6, 8, 10, 12 uses a shared global history table 18 which is indexed by respective branch history registers 20, 22 for each program thread. Different mappings are used between preceding branch behavior and the prediction value stored within respective branch history registers 20, 22. These different mappings may be provided by inverters placed into the shift in paths for the branch history registers 20, 22 or by adders 40, 42 or in some other way. The different mappings help to equalise the probability of use of the particular storage locations within the global history table 18 such that the plurality of program threads are not competing excessively for the same storage locations corresponding to the more commonly occurring patterns of preceding branch behavior.

Abstract: A branch prediction mechanism 16, 18 within a multithreaded processor having hardware scheduling logic 6, 8, 10, 12 uses a shared global history table 18 which is indexed by respective branch history registers 20, 22 for each program thread. Different mappings are used between preceding branch behaviour and the prediction value stored within respective branch history registers 20, 22. These different mappings may be provided by inverters placed into the shift in paths for the branch history registers 20, 22 or by adders 40, 42 or in some other way. The different mappings help to equalise the probability of use of the particular storage locations within the global history table 18 such that the plurality of program threads are not competing excessively for the same storage locations corresponding to the more commonly occurring patterns of preceding branch behaviour.

Abstract: A data processing apparatus, method and watch point unit are disclosed. The data processing apparatus comprises: a processor core operable to process a sequence of instructions; and a watch point unit operable to receive an indication of each of the sequence of instructions being processed by the processor core, the watch point unit being operable to determine whether the indication of each of the sequence of instructions correlates with at least one watch point condition and, if so, the watch point unit being further operable to provide an indication that the at least one watch point condition occurred. Accordingly, watch point conditions can be set based on the instructions themselves rather than being based on a likely effect of that instruction. This enables a wider range of conditions of interest to be defined which expands the usefulness of debugging.