Abstract: A semiconductor device includes a first element separation structure, a second element separation structure, and a third element separation structure sequentially disposed along a first direction and extending in a second direction intersecting the first direction; a first active pattern extending in the first direction between the first element separation structure and the second element separation structure; a second active pattern extending in the first direction between the second element separation structure and the third element separation structure and separated from the first active pattern by the second element separation structure; a first gate electrode extending in the second direction on the first active pattern; and a plurality of second gate electrodes extending in the second direction on the second active pattern, wherein a width of the first active pattern in the second direction is greater than a width of the second active pattern in the second direction.

Abstract: A semiconductor device includes a substrate including an active region, a first gate line and a second gate line in the active region, a first source/drain contact pattern in the active region at one side of the first gate line, a second source/drain contact pattern in the active region at one side of the second gate line, and a dummy source/drain contact pattern in the active region between the first gate line and the second gate line. The first gate line and the second gate line may be spaced apart from each other in the first direction and may extend in the second direction. The second direction may cross the first direction. A size of the dummy source/drain contact pattern may be less than a size of the first source/drain contact pattern and a size of the second source/drain contact pattern.

Abstract: A semiconductor device includes at least one active pattern on a substrate, at least one gate electrode intersecting the at least one active pattern, source/drain regions on the at least one active pattern, the source/drain regions being on opposite sides of the at least one gate electrode, and a barrier layer between at least one of the source/drain regions and the at least one active pattern, the barrier layer being at least on bottoms of the source/drain regions and including oxygen.

Abstract: Disclosed is a semiconductor device comprising a substrate including PMOSFET and NMOSFET regions, first active fins at the PMOSFET region, second active fins at the NMOSFET region, a gate electrode extending in a first direction and running across the first and second active fins, a first source/drain pattern on the first active fins and connecting the first active fins to each other, a second source/drain pattern on the second active fins and connecting the second active fins to each other, a first active contact electrically connected to the first source/drain pattern, and a second active contact electrically connected to the second source/drain pattern. A maximum width of the first active contact in the first direction is less than a maximum width of the second active in the first direction.

Abstract: A semiconductor device includes at least one active pattern on a substrate, at least one gate electrode intersecting the at least one active pattern, source/drain regions on the at least one active pattern, the source/drain regions being on opposite sides of the at least one gate electrode, and a barrier layer between at least one of the source/drain regions and the at least one active pattern, the barrier layer being at least on bottoms of the source/drain regions and including oxygen.

Abstract: A semiconductor device includes at least one active pattern on a substrate, at least one gate electrode intersecting the at least one active pattern, source/drain regions on the at least one active pattern, the source/drain regions being on opposite sides of the at least one gate electrode, and a barrier layer between at least one of the source/drain regions and the at least one active pattern, the barrier layer being at least on bottoms of the source/drain regions and including oxygen.

Abstract: Disclosed is a semiconductor device comprising a substrate including PMOSFET and NMOSFET regions, first active fins at the PMOSFET region, second active fins at the NMOSFET region, a gate electrode extending in a first direction and running across the first and second active fins, a first source/drain pattern on the first active fins and connecting the first active fins to each other, a second source/drain pattern on the second active fins and connecting the second active fins to each other, a first active contact electrically connected to the first source/drain pattern, and a second active contact electrically connected to the second source/drain pattern. A maximum width of the first active contact in the first direction is less than a maximum width of the second active in the first direction .

Abstract: Provided are semiconductor devices having various line widths and a method of manufacturing the semiconductor device. The semiconductor device includes: a substrate including a first region and a second region, a plurality of first gate lines extending in a first direction in the first region and each having a first width in a second; a plurality of second gate lines extending in the first direction in the second region and each having a second width that is different from the first width in the second direction and a pitch that is the same as a pitch of the plurality of first gate lines; a spacer layer covering opposite side walls of each of the plurality of first gate lines and each of the plurality of second gate lines; and a first base layer arranged between the substrate and the spacer layer in the first region.

Abstract: Provided are semiconductor devices having various line widths and a method of manufacturing the semiconductor device. The semiconductor device includes: a substrate including a first region and a second region, a plurality of first gate lines extending in a first direction in the first region and each having a first width in a second; a plurality of second gate lines extending in the first direction in the second region and each having a second width that is different from the first width in the second direction and a pitch that is the same as a pitch of the plurality of first gate lines; a spacer layer covering opposite side walls of each of the plurality of first gate lines and each of the plurality of second gate lines; and a first base layer arranged between the substrate and the spacer layer in the first region.

Abstract: Provided are semiconductor devices having various line widths and a method of manufacturing the semiconductor device. The semiconductor device includes: a substrate including a first region and a second region, a plurality of first gate lines extending in a first direction in the first region and each having a first width in a second; a plurality of second gate lines extending in the first direction in the second region and each having a second width that is different from the first width in the second direction and a pitch that is the same as a pitch of the plurality of first gate lines; a spacer layer covering opposite side walls of each of the plurality of first gate lines and each of the plurality of second gate lines; and a first base layer arranged between the substrate and the spacer layer in the first region.

Abstract: A semiconductor device comprises: a substrate; a first well region of a first conductivity type and a second well region of a second conductivity type formed horizontally adjacent to each other in the substrate; a buried insulation layer formed on the first well region and the second well region; a first semiconductor layer formed to vertically overlap the first well region, and a second semiconductor layer formed to vertically overlap the second well region, on the buried insulation layer; a first isolation layer formed between the first semiconductor layer and the second semiconductor layer on the buried insulation layer; and a conductive layer formed on the first semiconductor layer and the second semiconductor layer to extend over the first semiconductor layer and the second semiconductor layer.

Abstract: Provided are semiconductor devices having various line widths and a method of manufacturing the semiconductor device. The semiconductor device includes: a substrate including a first region and a second region, a plurality of first gate lines extending in a first direction in the first region and each having a first width in a second; a plurality of second gate lines extending in the first direction in the second region and each having a second width that is different from the first width in the second direction and a pitch that is the same as a pitch of the plurality of first gate lines; a spacer layer covering opposite side walls of each of the plurality of first gate lines and each of the plurality of second gate lines; and a first base layer arranged between the substrate and the spacer layer in the first region.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including first through third regions, a first transistor of a first conductivity type disposed on the first region of the substrate and including a first channel layer, in which the first channel layer includes a first material, a second transistor of a second conductivity type different from the first conductivity type disposed on the second region of the substrate and including a second channel layer, in which the second channel layer includes the first material, and a third transistor of the second conductivity type disposed on the third region of the substrate and including a third channel layer, in which the third channel layer includes a second material different from the first material.

Abstract: A semiconductor device includes: a substrate including a first well region; a gate electrode disposed on the substrate; a semiconductor pattern disposed between the substrate and the gate electrode; a plurality of source/drain patterns disposed on the substrate and on opposing sides of the gate electrode; an impurity layer disposed in the substrate and between the semiconductor pattern and the first well region; and a barrier layer disposed in the substrate and between the semiconductor pattern and the impurity layer. The barrier layer includes oxygen.

Abstract: A semiconductor device comprises: a substrate; a first well region of a first conductivity type and a second well region of a second conductivity type formed horizontally adjacent to each other in the substrate; a buried insulation layer formed on the first well region and the second well region; a first semiconductor layer formed to vertically overlap the first well region, and a second semiconductor layer formed to vertically overlap the second well region, on the buried insulation layer; a first isolation layer formed between the first semiconductor layer and the second semiconductor layer on the buried insulation layer; and a conductive layer formed on the first semiconductor layer and the second semiconductor layer to extend over the first semiconductor layer and the second semiconductor layer.

Abstract: A semiconductor device including an active pattern on a substrate; a gate structure crossing the active pattern; a source/drain pattern on the active pattern at a side of the gate structure; a contact plug on the source/drain pattern; and a conductive pattern between the source/drain pattern and the contact plug, wherein the source/drain pattern includes a barrier layer adjacent to the conductive pattern, and wherein the barrier layer includes an oxygen atom.

Abstract: A semiconductor device includes at least one active pattern on a substrate, at least one gate electrode intersecting the at least one active pattern, source/drain regions on the at least one active pattern, the source/drain regions being on opposite sides of the at least one gate electrode, and a barrier layer between at least one of the source/drain regions and the at least one active pattern, the barrier layer being at least on bottoms of the source/drain regions and including oxygen.

Abstract: A semiconductor device includes a substrate including an active fin and an isolation layer thereon, a first gate structure on the active fin, the first gate structure including a first gate insulation layer pattern and a first metal pattern, and the first metal pattern having a first conductivity type and directly contacting the first gate insulation layer pattern, a first channel region at a portion of the active fin facing a bottom surface of the first gate structure, the first channel region including impurities having the first conductivity type, and first source/drain regions at upper portions of the active fin adjacent to opposite sidewalls of the first gate structure, the first source/drain regions including impurities having a second conductivity type different from the first conductivity type.

Abstract: A semiconductor device includes a substrate including an active fin and an isolation layer thereon, a first gate structure on the active fin, the first gate structure including a first gate insulation layer pattern and a first metal pattern, and the first metal pattern having a first conductivity type and directly contacting the first gate insulation layer pattern, a first channel region at a portion of the active fin facing a bottom surface of the first gate structure, the first channel region including impurities having the first conductivity type, and first source/drain regions at upper portions of the active fin adjacent to opposite sidewalls of the first gate structure, the first source/drain regions including impurities having a second conductivity type different from the first conductivity type.

Abstract: The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a first metal layer on the high k dielectric material layer; forming a silicon layer on the first metal layer; patterning the silicon layer, the first metal layer and the high k dielectric material layer to form a gate stack; and performing a silicidation process to fully change the silicon layer into a silicide electrode.