Abstract: An apparatus includes a plurality of decoding stages, each configured to perform a decoding iteration of an Error Correction Code (ECC), and control circuitry. The control circuitry is configured to receive two or more input signals that carry data encoded with the ECC, to adaptively select an allocation that specifies a respective number of decoding iterations of the ECC to be performed on each of the input signals, to configure the decoding stages in the plurality in one or more cascades in accordance with the allocation, and to decode the input signals using the cascaded decoding stages.

Abstract: A synchronizing circuit processes a plurality (N) of input signals to generate a synchronizing circuit output signal, and provides the synchronizing circuit output signal synchronous to a system clock, wherein the N input signals are asynchronous to the system clock. Input stage circuitry samples the N asynchronous input signals. Combinatorial logic circuitry receives and combines the sampled asynchronous input signals to generate the synchronizing circuit output signal. First polarity edge flip flop circuitry to receive, as first polarity edge flip flop input, a first output of at least a first portion of the combinatorial logic circuitry, wherein the first polarity edge flip flop circuitry processes the first polarity edge flip flop input responsive to a first polarity edge of the system clock signal to provide a first polarity edge processed output signal.