Patents by Inventor Yuri Ryabinin
Yuri Ryabinin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230410858Abstract: Various devices, such as storage devices or systems are configured to transmit data between various components over one or more interfaces. The operation of these interfaces is based on the mechanical limits of the components doing the communication, often latches. Latches often require a setup and hold time limit on the signal being transmitted to be held a desired value. Because the physical effects of the environment, such as voltage being provided, temperature of the component, for example, can affect the operation of the latch, there is often a large margin used to operate them. These large margins avoid errors but decrease overall speed of the interface. By utilizing a test latch within an interface bus group with a drop in operating voltage, changes in output detected can be indicative of upcoming errors. Once detected, the error can be remedied by increasing voltage, lowering operating speeds, or cooling the components.Type: ApplicationFiled: June 15, 2022Publication date: December 21, 2023Inventors: Mordekhay Zehavi, Mahmud Asfur, Yossef Tamir, Yuri Ryabinin
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Publication number: 20230342070Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller includes a decoder multiplexer (mux) module, a plurality of request/response channels coupled to the decoder mux module, an arithmetic pipeline module coupled to the plurality of request/response channels, an arbiter module coupled to the plurality of request/response channels and the arithmetic pipeline module, a mux/arbiter module coupled to the arithmetic pipeline module, a random access memory (RAM) access module coupled to the decoder mux module and the mux/arbiter module, and a RAM coupled to the mux/arbiter module. The controller is configured to determine a pipeline depth value and a calculation parallelism value of the arithmetic pipeline module and configure the arithmetic pipeline module based on the determining.Type: ApplicationFiled: April 22, 2022Publication date: October 26, 2023Inventors: Yuri RYABININ, Shay BENISTY
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Patent number: 11487544Abstract: The present disclosure generally relates to a method and device for simultaneously decoding data. Rather than sending data to be decoded to a single decoder, the data can be sent to multiple, available decoders so that the data can be decode in parallel. The data decoded from the first decoder that completes decoding of the data will be delivered to the host device. All remaining decoded data that was decoded in parallel will be discarded. The decoders operating simultaneously in parallel can operate using different parameters such as different calculation precision (power levels). By utilizing multiple decoders simultaneously in parallel, the full functionality of the data storage device's decoding capabilities are utilized without increasing latency.Type: GrantFiled: January 15, 2020Date of Patent: November 1, 2022Assignee: Western Digital Technologies, Inc.Inventors: Shay Benisty, Eran Banani, Yuri Ryabinin
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Patent number: 11190219Abstract: An error correcting code (ECC) decoder for a non-volatile memory device is configured to decode data stored by the non-volatile memory device using a parity check matrix with columns of different column weights. The ECC decoder is further configured to artificially slow processing of one or more of the columns of the parity check matrix in response to column weights for the one or more columns satisfying a threshold.Type: GrantFiled: June 30, 2020Date of Patent: November 30, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Ran Zamir, Dudy Avraham, Eran Sharon, Idan Alrod, Idan Goldenberg, Omer Fainzilber, Yuri Ryabinin, Yan Dumchin, Igal Mariasin, Eran Banani
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Publication number: 20210216326Abstract: The present disclosure generally relates to a method and device for simultaneously decoding data. Rather than sending data to be decoded to a single decoder, the data can be sent to multiple, available decoders so that the data can be decoded in parallel. The data decoded from the first decoder that completes decoding of the data will be delivered to the host device. All remaining decoded data that was decoded in parallel will be discarded. The decoders operating simultaneously in parallel can operate using different parameters such as different calculation precision (power levels). By utilizing multiple decoders simultaneously in parallel, the full functionality of the data storage device's decoding capabilities are utilized without increasing latency. As a result, quality of service (QoS) is improved.Type: ApplicationFiled: January 15, 2020Publication date: July 15, 2021Inventors: Shay BENISTY, Eran BANANI, Yuri RYABININ
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Patent number: 10565040Abstract: A device includes a non-volatile memory and a low density parity check (LDPC) decoder configured to receive a representation of a codeword from the non-volatile memory. The LDPC decoder includes multiple data processing units (DPUs) and a control circuit coupled to the DPUs. The control circuit is responsive to an error metric associated with the representation of the codeword and is configured to set a message resolution at least partially based on the error metric and to selectively disable one or more components of the LDPC decoder based on the message resolution.Type: GrantFiled: June 22, 2017Date of Patent: February 18, 2020Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Yuri Ryabinin, Yan Dumchin
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Patent number: 10530393Abstract: A device includes a low density parity check (LDPC) decoder that is configured to receive a representation of a codeword. The LDPC decoder includes a circuit configured to set a message length of a decoding message at least partially based on an error metric associated with the representation of the codeword. The LDPC decoder also includes a processing unit including a first group of components and a second group of components. The processing unit configured to selectively couple the first group of components to the second group of components based on the message length of the decoding message.Type: GrantFiled: June 29, 2017Date of Patent: January 7, 2020Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Yuri Ryabinin, Yan Dumchin
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Patent number: 10218384Abstract: A device includes a low density parity check (LDPC) decoder that configured to receive a representation of a codeword. The LDPC decoder includes a message memory configured to store decoding messages, multiple data processing units (DPUs), a control circuit, and a reording circuit. The control circuit is configured to enable a first number of the DPUs to decode the representation of the codeword in response to a decoding mode indicator indicating a first decoding mode and to enable a second number of the DPUs to decode the representation of the codeword in response to the decoding mode indicator indicating a second decoding mode. The reordering circuit is configured to selectively reorder at least one of the decoding messages based on the decoding mode indicator.Type: GrantFiled: December 1, 2016Date of Patent: February 26, 2019Assignee: SanDisk Technologies LLCInventors: Eran Sharon, Idan Goldenberg, Ishai Ilani, Idan Alrod, Yuri Ryabinin, Yan Dumchin, Mark Fiterman, Ran Zamir
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Patent number: 10180874Abstract: A data storage device may include a memory and a controller that includes an error correction coding (ECC) decoder configured to operate in a plurality of decoding modes. The controller also includes a bit error rate estimator configured to determine, based on data received from the memory, bit error rate estimates for ECC codewords from the memory. The controller also includes a data path management unit configured to reorder the codewords based on the bit error rate estimates and to provide the reordered codewords to the ECC decoder.Type: GrantFiled: June 5, 2017Date of Patent: January 15, 2019Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Alexander Bazarsky, Eran Sharon, Yuri Ryabinin, Yan Dumchin, Idan Alrod, Ariel Navon
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Publication number: 20180159555Abstract: A device includes a low density parity check (LDPC) decoder that is configured to receive a representation of a codeword. The LDPC decoder includes a circuit configured to set a message length of a decoding message at least partially based on an error metric associated with the representation of the codeword. The LDPC decoder also includes a processing unit including a first group of components and a second group of components. The processing unit configured to selectively couple the first group of components to the second group of components based on the message length of the decoding message.Type: ApplicationFiled: June 29, 2017Publication date: June 7, 2018Inventors: Yuri Ryabinin, Yan Dumchin
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Publication number: 20180157551Abstract: A device includes a non-volatile memory and a low density parity check (LDPC) decoder configured to receive a representation of a codeword from the non-volatile memory. The LDPC decoder includes multiple data processing units (DPUs) and a control circuit coupled to the DPUs. The control circuit is responsive to an error metric associated with the representation of the codeword and is configured to set a message resolution at least partially based on the error metric and to selectively disable one or more components of the LDPC decoder based on the message resolution.Type: ApplicationFiled: June 22, 2017Publication date: June 7, 2018Inventors: YURI RYABININ, YAN DUMCHIN
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Publication number: 20180159553Abstract: A device includes a low density parity check (LDPC) decoder that configured to receive a representation of a codeword. The LDPC decoder includes a message memory configured to store decoding messages, multiple data processing units (DPUs), a control circuit, and a reording circuit. The control circuit is configured to enable a first number of the DPUs to decode the representation of the codeword in response to a decoding mode indicator indicating a first decoding mode and to enable a second number of the DPUs to decode the representation of the codeword in response to the decoding mode indicator indicating a second decoding mode. The reordering circuit is configured to selectively reorder at least one of the decoding messages based on the decoding mode indicator.Type: ApplicationFiled: December 1, 2016Publication date: June 7, 2018Inventors: ERAN SHARON, IDAN GOLDENBERG, ISHAI ILANI, IDAN ALROD, YURI RYABININ, YAN DUMCHIN, MARK FITERMAN, RAN ZAMIR
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Publication number: 20180159556Abstract: A device includes a low density parity check (LDPC) decoder that configured to receive a representation of a codeword. The LDPC decoder includes multiple data processing units (DPUs) and a control circuit. The control circuit is responsive to a decoding mode indicator and to an error metric and is configured to configure the DPUs according to a decoding mode indicated by the decoding mode indicator. The control circuit is further configured to selectively set a reduced-power configuration of one or more components of the LDPC decoder at least partially based on the error metric.Type: ApplicationFiled: June 5, 2017Publication date: June 7, 2018Inventors: Yan Dumchin, Yuri Ryabinin
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Patent number: 9905314Abstract: A storage module and method for datapath bypass are disclosed. In one embodiment, a storage module begins to perform a read operation that reads a set of code words from the memory and attempts to perform an error detection and correction operation on one of the read code words. In response to determining that the code word has an uncorrectable error, the storage module reads the other code words in the set but bypasses the error detection and correction operation on those other code words. The code word that had the uncorrectable error and the other code words are re-read, wherein at least the code word with the uncorrectable error is re-read with a different read condition. The storage module then attempts to perform the error detection and correction operation on the re-read code words. Other embodiments are provided.Type: GrantFiled: October 9, 2014Date of Patent: February 27, 2018Assignee: SanDisk Technologies LLCInventors: Daniel E. Tuers, Yoav Weinberg, Yuri Ryabinin
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Patent number: 9886342Abstract: A data storage device may include a non-volatile memory and a controller. According to a first aspect, a bit error rate (BER) estimate may be determined at a memory interface of the controller based on hard bit data from the non-volatile memory. The BER estimate may be used to determine, prior to transfer of the hard bit data to an error correction coding (ECC) decoder of the controller, whether to request transfer of soft bit data from the non-volatile memory. According to a second aspect, the ECC decoder may be instructed to initiate decoding of a codeword or sub code using a particular operating mode based on the BER estimate for the codeword or sub code. According to a third aspect, sub codes of an ECC codeword may be reordered based on BER estimates for the sub codes, and the reordered sub codes may be provided to the ECC decoder.Type: GrantFiled: October 28, 2015Date of Patent: February 6, 2018Assignee: SanDisk Technologies LLCInventors: Yuri Ryabinin, Eran Banani, Yan Dumchin, Mark Naumenko, Alexander Mostovoy, Mark Fiterman
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Publication number: 20170269991Abstract: A data storage device may include a memory and a controller that includes an error correction coding (ECC) decoder configured to operate in a plurality of decoding modes. The controller also includes a bit error rate estimator configured to determine, based on data received from the memory, bit error rate estimates for ECC codewords from the memory. The controller also includes a data path management unit configured to reorder the codewords based on the bit error rate estimates and to provide the reordered codewords to the ECC decoder.Type: ApplicationFiled: June 5, 2017Publication date: September 21, 2017Inventors: Alexander Bazarsky, ERAN SHARON, YURI RYABININ, YAN DUMCHIN, IDAN ALROD, ARIEL NAVON
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Patent number: 9768807Abstract: A decoder includes syndrome storage and a first barrel shifter configured to bit-shift hard decision bit data to generate shifted data that is aligned with a set of syndromes from the syndrome storage. The decoder also includes a first syndrome update circuit coupled to the first barrel shifter and configured to process the set of syndromes based on the shifted data to generate an updated version of the set of syndromes. The decoder may also be configured to perform on-the-fly syndrome weight computation.Type: GrantFiled: August 31, 2015Date of Patent: September 19, 2017Assignee: SanDisk Technologies LLCInventors: Xinmiao Zhang, Yuri Ryabinin, Eran Sharon
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Publication number: 20170123898Abstract: A data storage device may include a non-volatile memory and a controller. According to a first aspect, a bit error rate (BER) estimate may be determined at a memory interface of the controller based on hard bit data from the non-volatile memory. The BER estimate may be used to determine, prior to transfer of the hard bit data to an error correction coding (ECC) decoder of the controller, whether to request transfer of soft bit data from the non-volatile memory. According to a second aspect, the ECC decoder may be instructed to initiate decoding of a codeword or sub code using a particular operating mode based on the BER estimate for the codeword or sub code. According to a third aspect, sub codes of an ECC codeword may be reordered based on BER estimates for the sub codes, and the reordered sub codes may be provided to the ECC decoder.Type: ApplicationFiled: October 28, 2015Publication date: May 4, 2017Inventors: Yuri Ryabinin, Eran Banani, Yan Dumchin, Mark Naumenko, Alexander Mostovoy, Mark Fiterman
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Publication number: 20170063400Abstract: A decoder includes syndrome storage and a first barrel shifter configured to bit-shift hard decision bit data to generate shifted data that is aligned with a set of syndromes from the syndrome storage. The decoder also includes a first syndrome update circuit coupled to the first barrel shifter and configured to process the set of syndromes based on the shifted data to generate an updated version of the set of syndromes. The decoder may also be configured to perform on-the-fly syndrome weight computation.Type: ApplicationFiled: August 31, 2015Publication date: March 2, 2017Inventors: XINMIAO ZHANG, YURI RYABININ, ERAN SHARON
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Publication number: 20160103732Abstract: A storage module and method for datapath bypass are disclosed. In one embodiment, a storage module begins to perform a read operation that reads a set of code words from the memory and attempts to perform an error detection and correction operation on one of the read code words. In response to determining that the code word has an uncorrectable error, the storage module reads the other code words in the set but bypasses the error detection and correction operation on those other code words. The code word that had the uncorrectable error and the other code words are re-read, wherein at least the code word with the uncorrectable error is re-read with a different read condition. The storage module then attempts to perform the error detection and correction operation on the re-read code words. Other embodiments are provided.Type: ApplicationFiled: October 9, 2014Publication date: April 14, 2016Applicant: SanDisk Technologies Inc.Inventors: Daniel E. Tuers, Yoav Weinberg, Yuri Ryabinin