Patents by Inventor Yuri Uritsky

Yuri Uritsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8569692
    Abstract: A method of operation of a measurement system includes: providing a specimen having a film; controlling a beam generator to direct a charged particle beam into the specimen; detecting a reference signal emitted from the specimen; normalizing the reference signal to create a film L-ratio; and determining a thickness of the film by correlating the film L-ratio to a calibration curve.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: October 29, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Biao Liu, Chikuang Wang, Yuri Uritsky
  • Patent number: 7601648
    Abstract: Methods for forming a integrated gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate. In another embodiment, the method includes precleaning a substrate, forming a silicon oxide layer on the substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate, wherein the formed silicon oxide layer and the silicon nitride layer has a total thickness less than 30 ? utilized as a gate dielectric layer in a gate structure.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: October 13, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Thai Cheng Chua, Shankar Muthukrisnan, Johanes Swenberg, Shreyas Kher, Chikuang Charles Wang, Giuseppina Conti, Yuri Uritsky
  • Publication number: 20080026553
    Abstract: Methods for forming a integrated gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate. In another embodiment, the method includes precleaning a substrate, forming a silicon oxide layer on the substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate, wherein the formed silicon oxide layer and the silicon nitride layer has a total thickness less than 30 ? utilized as a gate dielectric layer in a gate structure.
    Type: Application
    Filed: July 31, 2006
    Publication date: January 31, 2008
    Inventors: Thai Cheng Chua, Shankar Muthukrisnan, Johanes Swenberg, Shreyas Kher, Chikuang Charles Wang, Giuseppina Conti, Yuri Uritsky
  • Patent number: 6122562
    Abstract: A method and apparatus that accurately marks a wafer at selected locations such as a defect location on the surface of a wafer such that a wafer analysis system (e.g., SEM or AFM) may rapidly find the defect. The apparatus contains a wafer platen for retaining a wafer in a substantially horizontal orientation and a marking assembly mounted above the wafer platen. The marking assembly further contains an optical microscope and a marking head. In operation, a user locates a defect using the optical microscope and places a pattern of fiducial marks at a predetermined distance from the defect, e.g., four marks in a diamond pattern circumscribing the defect.
    Type: Grant
    Filed: May 5, 1997
    Date of Patent: September 19, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Patrick D. Kinney, Yuri Uritsky, Nagaraja Rao
  • Patent number: 6051845
    Abstract: A method and apparatus that accurately marks a wafer at selected locations to form a wafer coordinate system. The apparatus contains a wafer platen for retaining a wafer in a substantially horizontal orientation, a wafer orientation detector assembly and a marking assembly mounted above the wafer platen. In operation, the apparatus orients the wafer by identifying an orientation attribute of the wafer, then applies fiducial marks to the wafer. The wafer marking apparatus forms a portion of an integrated analytical tool.
    Type: Grant
    Filed: March 25, 1998
    Date of Patent: April 18, 2000
    Assignee: Applied Materials, Inc.
    Inventor: Yuri Uritsky
  • Patent number: 5985680
    Abstract: A method and apparatus for accurately transforming coordinates within a first coordinate system (e.g., a two-dimensional coordinate system associated with a substrate (or portion thereof)) into coordinates in a second coordinate system (e.g., a three-dimensional coordinate system of substrate (or portion thereof) tilted within a wafer analysis tool.
    Type: Grant
    Filed: August 8, 1997
    Date of Patent: November 16, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Ajay Singhal, Yuri Uritsky, Patrick D. Kinney
  • Patent number: 5870187
    Abstract: An automated method for aligning wafer surface scan maps and locating defects such as particle contaminant distributions on a wafer surface. More specifically, the invention is an automated method for locating added and removed contaminants and other defects on a semiconductor wafer surface after the wafer has undergone wafer-handling and/or processing. A second data set of a second scan of a wafer surface is misalignment-corrected to a first coordinate system of a first scan of the wafer surface. Thereafter, a final match is made between a first data set of the first scan and the misalignment-corrected data of the second scan. Non-matching locations in the misalignment-corrected data of the second scan represent added defects on the surface of the wafer. Non-matching locations in the base data of the first scan represent removed defects from the surface of the wafer.
    Type: Grant
    Filed: August 8, 1997
    Date of Patent: February 9, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Yuri Uritsky, Patrick D. Kinney, Man-Ping Cai
  • Patent number: 5474640
    Abstract: An apparatus suitable for marking a substrate comprises a holder for holding a substrate and a ground for electrically grounding the substrate. At least one needle electrode has a tip located proximate to the substrate so that there is a gap between the substrate and the tip. A high voltage source provides a current to the electrode tip to ionize the gas in the gap so that the ionized gas can impinge upon and mark the substrate.
    Type: Grant
    Filed: July 19, 1993
    Date of Patent: December 12, 1995
    Assignee: Applied Materials, Inc.
    Inventors: Yan Ye, Anand Gupta, Yuri Uritsky