Patents by Inventor Yurika Sato

Yurika Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10670277
    Abstract: Provided is an oven having an improved structure for keeping a cooking chamber clean. The oven includes a main body, a cooking chamber provided inside the main body, a main heater disposed inside the cooking chamber, a fan disposed inside the cooking chamber to circulate air heated by the main heater, a coating film formed on at least a part of a cooking chamber inner wall and having a liquid repellency, and a contaminant collecting portion having a liquid repellency smaller than that of the coating film and provided on the cooking chamber inner wall with which air circulated by the fan collides.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: June 2, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kiyoshi Iwamoto, Yasushi Urai, Shigeki Hayashi, Seiji Sato, Toshihiro Doi, Kazutoshi Takenoshita, Yurika Kida
  • Patent number: 9131171
    Abstract: Provided is an image sensor having a pixel includes a photoelectric conversion element; a capacitor which is connected between the photoelectric conversion element; a reset circuit which resets a potential of a node between the photoelectric conversion element and the capacitor; an amplifier circuit which outputs a signal corresponding to the potential of the node; and a switch which controls electrical conduction between the amplifier circuit and a vertical signal line. When the node is brought into an electrically floating state, the potential of the optical signal is stored in the node in a state of being inverted. When an optical signal is detected while the potential is stored in the node, the potential of the node increases in accordance with an output potential of the photoelectric conversion element, and thus the potential of the node corresponds to a difference in potential between the optical signals in different light-receiving periods.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: September 8, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Aoki, Takayuki Ikeda, Yurika Sato, Koji Dairiki
  • Patent number: 8664722
    Abstract: In a method for manufacturing a semiconductor device, a semiconductor film formed over an insulator is doped with an impurity element to a depth less than the thickness of the semiconductor film, thereby forming an impurity doped layer; a metal silicide layer is formed on the impurity doped layer; the metal silicide layer and the semiconductor film are etched to form a recessed portion; and a layer which is not doped with the impurity element and is located at the bottom of the recessed portion of the semiconductor film is thinned to make a channel formation region. Further, a gate electrode is formed in the recessed portion over the thinned non impurity doped layer, with an insulating film interposed therebetween.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: March 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takashi Shingu, Daisuke Ohgarane, Yurika Sato
  • Patent number: 8431451
    Abstract: A semiconductor substrate is formed into a regular hexagon or a shape similar to the regular hexagon. The semiconductor substrate is bonded to and separated from a large-area substrate. Moreover, layout is designed so that a boundary of bonded semiconductors is located in a region which is removed by etching when patterning is performed by photolithography or the like.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: April 30, 2013
    Assignee: Semicondutor Energy Laboratory Co., Ltd.
    Inventors: Yasunori Yoshida, Akihisa Shimomura, Yurika Sato
  • Publication number: 20120049276
    Abstract: In a method for manufacturing a semiconductor device, a semiconductor film formed over an insulator is doped with an impurity element to a depth less than the thickness of the semiconductor film, thereby forming an impurity doped layer; a metal silicide layer is formed on the impurity doped layer; the metal silicide layer and the semiconductor film are etched to form a recessed portion; and a layer which is not doped with the impurity element and is located at the bottom of the recessed portion of the semiconductor film is thinned to make a channel formation region. Further, a gate electrode is formed in the recessed portion over the thinned non impurity doped layer, with an insulating film interposed therebetween.
    Type: Application
    Filed: November 4, 2011
    Publication date: March 1, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Takashi SHINGU, Daisuke Ohgarane, Yurika Sato
  • Patent number: 8053289
    Abstract: In a method for manufacturing a semiconductor device, a semiconductor film formed over an insulator is doped with an impurity element to a depth less than the thickness of the semiconductor film, thereby forming an impurity doped layer; a metal silicide layer is formed on the impurity doped layer; the metal silicide layer and the semiconductor film are etched to form a recessed portion; and a layer which is not doped with the impurity element and is located at the bottom of the recessed portion of the semiconductor film is thinned to make a channel formation region. Further, a gate electrode is formed in the recessed portion over the thinned non impurity doped layer, with an insulating film interposed therebetween.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: November 8, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takashi Shingu, Daisuke Ohgarane, Yurika Sato
  • Patent number: 7795111
    Abstract: An effect of metal contamination caused in manufacturing an SOI substrate can is suppressed. A damaged region is formed by irradiating a semiconductor substrate with hydrogen ions, and then, a base substrate and the semiconductor substrate are bonded to each other. Heat treatment is performed thereon to cleave the semiconductor substrate, so that an SOI substrate is manufactured. A gettering site layer is formed of a semiconductor containing a Group 18 element such as Ar, over a semiconductor layer of the SOI substrate. Heat treatment is performed thereon to perform gettering of a metal element in the semiconductor layer with the gettering site layer. By removing the gettering site layer by etching, thinning of the semiconductor layer can be performed.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: September 14, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Hidekazu Miyairi, Yurika Sato
  • Publication number: 20090096024
    Abstract: In a method for manufacturing a semiconductor device, a semiconductor film formed over an insulator is doped with an impurity element to a depth less than the thickness of the semiconductor film, thereby forming an impurity doped layer; a metal silicide layer is formed on the impurity doped layer; the metal silicide layer and the semiconductor film are etched to form a recessed portion; and a layer which is not doped with the impurity element and is located at the bottom of the recessed portion of the semiconductor film is thinned to make a channel formation region. Further, a gate electrode is formed in the recessed portion over the thinned non impurity doped layer, with an insulating film interposed therebetween.
    Type: Application
    Filed: October 15, 2008
    Publication date: April 16, 2009
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Takashi SHINGU, Daisuke OHGARANE, Yurika SATO
  • Publication number: 20090001469
    Abstract: A semiconductor substrate is formed into a regular hexagon or a shape similar to the regular hexagon. The semiconductor substrate is bonded to and separated from a large-area substrate. Moreover, layout is designed so that a boundary of bonded semiconductors is located in a region which is removed by etching when patterning is performed by photolithography or the like.
    Type: Application
    Filed: June 24, 2008
    Publication date: January 1, 2009
    Inventors: Yasunori Yoshida, Akihisa Shimomura, Yurika Sato
  • Publication number: 20090004821
    Abstract: An effect of metal contamination caused in manufacturing an SOI substrate can is suppressed. A damaged region is formed by irradiating a semiconductor substrate with hydrogen ions, and then, a base substrate and the semiconductor substrate are bonded to each other. Heat treatment is performed thereon to cleave the semiconductor substrate, so that an SOI substrate is manufactured. A gettering site layer is formed of a semiconductor containing a Group 18 element such as Ar, over a semiconductor layer of the SOI substrate. Heat treatment is performed thereon to perform gettering of a metal element in the semiconductor layer with the gettering site layer. By removing the gettering site layer by etching, thinning of the semiconductor layer can be performed.
    Type: Application
    Filed: June 18, 2008
    Publication date: January 1, 2009
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Akihisa SHIMOMURA, Hidekazu MIYAIRI, Yurika SATO