Patents by Inventor Yurika Sato
Yurika Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240119173Abstract: An information transaction device is connected to an information holding device including a storage unit storing personal information and includes a sharing approval reception unit configured to receive approval of sharing of the personal information by an information sharing destination device from a user associated with the personal information, a provision approval reception unit configured to receive approval of provision which is transmission of the personal information to an information provision destination device, from the user associated with the personal information, a sharing instruction unit configured to, in a case where the sharing approval reception unit receives the approval of the sharing, instruct the information holding device to perform the sharing, and a provision instruction unit configured to, in a case where the provision approval reception unit receives the approval of the provision, instruct the information holding device to perform the provision.Type: ApplicationFiled: October 7, 2020Publication date: April 11, 2024Applicant: NEC CorporationInventors: Yusuke SATO, Yasumasa MITSUHATA, Masashi INOUE, Yurika MICHISHITA
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Publication number: 20240104080Abstract: An information transaction device stores catalog information including detailed information related to one or more datasets including personal information providable to an information provision destination device from an information provision source device. The information transaction device receives a provision request for the dataset from the information provision destination device. The information transaction device outputs a transmission request for the dataset indicated by the provision request to the information provision source device.Type: ApplicationFiled: October 7, 2020Publication date: March 28, 2024Applicant: NEC CorporationInventors: Yusuke SATO, Yasumasa Mitsuhata, Masashi Inoue, Yurika Michishita
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Patent number: 9131171Abstract: Provided is an image sensor having a pixel includes a photoelectric conversion element; a capacitor which is connected between the photoelectric conversion element; a reset circuit which resets a potential of a node between the photoelectric conversion element and the capacitor; an amplifier circuit which outputs a signal corresponding to the potential of the node; and a switch which controls electrical conduction between the amplifier circuit and a vertical signal line. When the node is brought into an electrically floating state, the potential of the optical signal is stored in the node in a state of being inverted. When an optical signal is detected while the potential is stored in the node, the potential of the node increases in accordance with an output potential of the photoelectric conversion element, and thus the potential of the node corresponds to a difference in potential between the optical signals in different light-receiving periods.Type: GrantFiled: February 21, 2013Date of Patent: September 8, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takeshi Aoki, Takayuki Ikeda, Yurika Sato, Koji Dairiki
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Patent number: 8664722Abstract: In a method for manufacturing a semiconductor device, a semiconductor film formed over an insulator is doped with an impurity element to a depth less than the thickness of the semiconductor film, thereby forming an impurity doped layer; a metal silicide layer is formed on the impurity doped layer; the metal silicide layer and the semiconductor film are etched to form a recessed portion; and a layer which is not doped with the impurity element and is located at the bottom of the recessed portion of the semiconductor film is thinned to make a channel formation region. Further, a gate electrode is formed in the recessed portion over the thinned non impurity doped layer, with an insulating film interposed therebetween.Type: GrantFiled: November 4, 2011Date of Patent: March 4, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takashi Shingu, Daisuke Ohgarane, Yurika Sato
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Patent number: 8431451Abstract: A semiconductor substrate is formed into a regular hexagon or a shape similar to the regular hexagon. The semiconductor substrate is bonded to and separated from a large-area substrate. Moreover, layout is designed so that a boundary of bonded semiconductors is located in a region which is removed by etching when patterning is performed by photolithography or the like.Type: GrantFiled: June 24, 2008Date of Patent: April 30, 2013Assignee: Semicondutor Energy Laboratory Co., Ltd.Inventors: Yasunori Yoshida, Akihisa Shimomura, Yurika Sato
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Publication number: 20120049276Abstract: In a method for manufacturing a semiconductor device, a semiconductor film formed over an insulator is doped with an impurity element to a depth less than the thickness of the semiconductor film, thereby forming an impurity doped layer; a metal silicide layer is formed on the impurity doped layer; the metal silicide layer and the semiconductor film are etched to form a recessed portion; and a layer which is not doped with the impurity element and is located at the bottom of the recessed portion of the semiconductor film is thinned to make a channel formation region. Further, a gate electrode is formed in the recessed portion over the thinned non impurity doped layer, with an insulating film interposed therebetween.Type: ApplicationFiled: November 4, 2011Publication date: March 1, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Takashi SHINGU, Daisuke Ohgarane, Yurika Sato
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Patent number: 8053289Abstract: In a method for manufacturing a semiconductor device, a semiconductor film formed over an insulator is doped with an impurity element to a depth less than the thickness of the semiconductor film, thereby forming an impurity doped layer; a metal silicide layer is formed on the impurity doped layer; the metal silicide layer and the semiconductor film are etched to form a recessed portion; and a layer which is not doped with the impurity element and is located at the bottom of the recessed portion of the semiconductor film is thinned to make a channel formation region. Further, a gate electrode is formed in the recessed portion over the thinned non impurity doped layer, with an insulating film interposed therebetween.Type: GrantFiled: October 15, 2008Date of Patent: November 8, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takashi Shingu, Daisuke Ohgarane, Yurika Sato
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Patent number: 7795111Abstract: An effect of metal contamination caused in manufacturing an SOI substrate can is suppressed. A damaged region is formed by irradiating a semiconductor substrate with hydrogen ions, and then, a base substrate and the semiconductor substrate are bonded to each other. Heat treatment is performed thereon to cleave the semiconductor substrate, so that an SOI substrate is manufactured. A gettering site layer is formed of a semiconductor containing a Group 18 element such as Ar, over a semiconductor layer of the SOI substrate. Heat treatment is performed thereon to perform gettering of a metal element in the semiconductor layer with the gettering site layer. By removing the gettering site layer by etching, thinning of the semiconductor layer can be performed.Type: GrantFiled: June 18, 2008Date of Patent: September 14, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Akihisa Shimomura, Hidekazu Miyairi, Yurika Sato
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Publication number: 20090096024Abstract: In a method for manufacturing a semiconductor device, a semiconductor film formed over an insulator is doped with an impurity element to a depth less than the thickness of the semiconductor film, thereby forming an impurity doped layer; a metal silicide layer is formed on the impurity doped layer; the metal silicide layer and the semiconductor film are etched to form a recessed portion; and a layer which is not doped with the impurity element and is located at the bottom of the recessed portion of the semiconductor film is thinned to make a channel formation region. Further, a gate electrode is formed in the recessed portion over the thinned non impurity doped layer, with an insulating film interposed therebetween.Type: ApplicationFiled: October 15, 2008Publication date: April 16, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Takashi SHINGU, Daisuke OHGARANE, Yurika SATO
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Publication number: 20090001469Abstract: A semiconductor substrate is formed into a regular hexagon or a shape similar to the regular hexagon. The semiconductor substrate is bonded to and separated from a large-area substrate. Moreover, layout is designed so that a boundary of bonded semiconductors is located in a region which is removed by etching when patterning is performed by photolithography or the like.Type: ApplicationFiled: June 24, 2008Publication date: January 1, 2009Inventors: Yasunori Yoshida, Akihisa Shimomura, Yurika Sato
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Publication number: 20090004821Abstract: An effect of metal contamination caused in manufacturing an SOI substrate can is suppressed. A damaged region is formed by irradiating a semiconductor substrate with hydrogen ions, and then, a base substrate and the semiconductor substrate are bonded to each other. Heat treatment is performed thereon to cleave the semiconductor substrate, so that an SOI substrate is manufactured. A gettering site layer is formed of a semiconductor containing a Group 18 element such as Ar, over a semiconductor layer of the SOI substrate. Heat treatment is performed thereon to perform gettering of a metal element in the semiconductor layer with the gettering site layer. By removing the gettering site layer by etching, thinning of the semiconductor layer can be performed.Type: ApplicationFiled: June 18, 2008Publication date: January 1, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Akihisa SHIMOMURA, Hidekazu MIYAIRI, Yurika SATO