Abstract: In an instruction processing unit, a first register group having at least one register whose bit width is enough for designating a desired address in the entire address space of a memory, and a second register group having at least one register whose bit width is not enough for said purpose, and operation means are provided. This operation means further includes first and second address generation means. In this unit, the first address generation means creates a desired operand address according to values stored in one or more registers in the first register group. The second address generation means creates an operand address to designate a desired partial space of the memory, by extending the bit width of a register in the second register group by a required amount.

Abstract: A microprocessor having a register bank architecture has n register banks, a memory, a bus for connecting the register bank and the memory, and a bank controller for controlling store/load operations between the register banks and the memory. The controller has a current bank pointer indicating data region of the register banks and the memory during the data store/load operations, and a bank size designation register indicating a bank size to be stored/loaded during the store/load operations. When an address of the current bank pointer is set in an destination operand in an instruction, the controller receives the contents of the current bank pointer and bank size designation register.

Abstract: A data-processing device has a clock generator for generating pulse signals .phi.1 and .phi.2, an ALU capable of executing various arithmetic-logic operations during cycles corresponding to the pulse signals .phi.1 and .phi.2,and a control unit for generating a control signal which causes the ALU to execute an arithmetic-logic operation according to an instruction. This data-processing device further includes a transfer switch for causing the ALU to execute an arithmetic-logic operation, which is for generating output data equal to input data, during a cycle in which the ALU would otherwise be idle.

Abstract: A LAN controller includes a memory device for storing data being received and transmitted by a microprocessor, data relating to data identification of said receiving and transmitting data, and data allowing/prohibiting the communication of said receiving and transmitting data, respectively, and a controller for automatically storing data allowing/prohibiting the communication of said receiving and transmitting data to said memory device when data relating to data identification of said receiving and transmitting data is stored into said memory device.