Patents by Inventor Yuri Komori

Yuri Komori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11070622
    Abstract: According to an embodiment, a client includes a street information collection unit for collecting street information near an arrangement place, a provision determination unit for determining whether the street information collected by the street information collection unit is information required to be provided to the server, and a first transmission unit for transmitting the street information, which is determined to be required to be provided by determination of the provision determination unit, to the server, with client identification information for identifying the client.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: July 20, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, Toshiba Infrastructure Systems & Solutions Corporation
    Inventors: Shinichi Kurihara, Hiroyuki Abe, Daisuke Takasaki, Shingo Yasunami, Hideki Ueno, Yasuo Ooya, Sunao Wada, Yuri Komori
  • Publication number: 20180198865
    Abstract: According to an embodiment, a client includes a street information collection unit for collecting street information near an arrangement place, a provision determination unit for determining whether the street information collected by the street information collection unit is information required to be provided to the server, and a first transmission unit for transmitting the street information, which is determined to be required to be provided by determination of the provision determination unit, to the server, with client identification information for identifying the client.
    Type: Application
    Filed: March 9, 2018
    Publication date: July 12, 2018
    Applicants: KABUSHIKI KAISHA TOSHIBA, Toshiba Infrastructure Systems & Solutions Corporation
    Inventors: Shinichi KURIHARA, Hiroyuki Abe, Daisuke Takasaki, Shingo Yasunami, Hideki Ueno, Yasuo Ooya, Sunao Wada, Yuri Komori
  • Patent number: 7915878
    Abstract: A switching regulator includes an inverter circuit and a size adjustment circuit. The inverter circuit converts an input voltage into an output voltage by a switching operation of a switch circuit. The size adjustment circuit controls an ON resistance of the switch circuit, depending on a power efficiency that is calculated from an input power dependent on the input voltage and an output power dependent on the output voltage.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: March 29, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Yuri Komori
  • Publication number: 20090001949
    Abstract: A switching regulator includes an inverter circuit and a size adjustment circuit. The inverter circuit converts an input voltage into an output voltage by a switching operation of a switch circuit. The size adjustment circuit controls an ON resistance of the switch circuit, depending on a power efficiency that is calculated from an input power dependent on the input voltage and an output power dependent on the output voltage.
    Type: Application
    Filed: June 27, 2008
    Publication date: January 1, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Yuri KOMORI
  • Patent number: 7238992
    Abstract: In a semiconductor integrated circuit for a DC—DC converter, an nMOS-type transistor Qn of a CMOS inverter 1c constituting a driver 1 is electrically floated from a substrate 12 through an n-type well region 11. Thus, the nMOS-type transistor Qn is electrically insulated from other transistors such as an npn-type transistor Q1 and an L-pnp-type transistor Q2 constituting a feedback control system 9 through the n-type well region 11. Stable operation is performed with a minute current without producing a malfunction caused by the influence of a parasitic current, even if the drain potential of an nMOS-type transistor is reduced to the ground potential or lower at the time of switching by a driver constituted from a CMOS inverter, to facilitate lower power consumption and higher efficiency, and also to eliminate a constraint on layout design of components.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: July 3, 2007
    Assignee: NEC Electronics Corporation
    Inventors: Yuri Komori, Kazuo Mitsui
  • Publication number: 20050151525
    Abstract: In a semiconductor integrated circuit for a DC-DC converter, an nMOS-type transistor Qn of a CMOS inverter 1c constituting a driver 1 is electrically floated from a substrate 12 through an n-type well region 11. Thus, the nMOS-type transistor Qn is electrically insulated from other transistors such as an npn-type transistor Q1 and an L-pnp-type transistor Q2 constituting a feedback control system 9 through the n-type well region 11. Stable operation is performed with a minute current without producing a malfunction caused by the influence of a parasitic current, even if the drain potential of an nMOS-type transistor is reduced to the ground potential or lower at the time of switching by a driver constituted from a CMOS inverter, to facilitate lower power consumption and higher efficiency, and also to eliminate a constraint on layout design of components.
    Type: Application
    Filed: January 14, 2005
    Publication date: July 14, 2005
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Yuri Komori, Kazuo Mitsui