Patents by Inventor Yusaku Kashiwagi
Yusaku Kashiwagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11041239Abstract: A method for forming a SiC film on a target substrate by ALD, comprises: activating a surface of the target substrate by activation gas plasma which is plasmatized an activation gas; and forming a SiC film by supplying a source gas containing a precursor represented by a chemical formula RSiX13 or RSiHClX2 onto the target substrate whose the surface is activated by activating the surface of the target substrate, where, R is an organic group having an unsaturated bond, X1 is selected from a group consisting of H, F, Cl, Br and I, and X2 is one selected from a group consisting of Cl, Br and I.Type: GrantFiled: November 16, 2017Date of Patent: June 22, 2021Assignee: TOKYO ELECTRON LIMITEDInventors: Taiki Katou, Shuji Azumo, Yusaku Kashiwagi
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Patent number: 10833166Abstract: A semiconductor device has an MIS structure that includes a semiconductor layer, a gate insulating film on the semiconductor layer, and a gate electrode on the gate insulating film. The gate insulating film has a layered structure that includes a base SiO2 layer and a high-k layer on the base SiO2 layer and containing Hf. The gate electrode has a portion made of a metal material having a work function of higher than 4.6 eV, the portion being in contact with at least the high-k layer.Type: GrantFiled: July 13, 2017Date of Patent: November 10, 2020Assignee: ROHM CO., LTD.Inventors: Kenji Yamamoto, Masatoshi Aketa, Hirokazu Asahara, Takashi Nakamura, Takuji Hosoi, Heiji Watanabe, Takayoshi Shimura, Shuji Azumo, Yusaku Kashiwagi
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Publication number: 20200063262Abstract: A method for forming a SiC film on a target substrate by ALD, comprises: activating a surface of the target substrate by activation gas plasma which is plasmatized an activation gas; and forming a SiC film by supplying a source gas containing a precursor represented by a chemical formula RSiX13 or RSiHClX2 onto the target substrate whose the surface is activated by activating the surface of the target substrate, where, R is an organic group having an unsaturated bond, X1 is selected from a group consisting of H, F, Cl, Br and I, and X2 is one selected from a group consisting of Cl, Br and I.Type: ApplicationFiled: November 16, 2017Publication date: February 27, 2020Inventors: Taiki KATOU, Shuji AZUMO, Yusaku KASHIWAGI
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Patent number: 10490443Abstract: A method of selectively forming a thin film on a substrate to be processed in which a conductive film and an insulating film are exposed to a surface of the substrate includes: selectively forming a first Ru film only on a first surface, which is an exposed surface of the conductive film and formed of one of Ru, RuO2, Pt, Pd, CuO, and CuO2, using an Ru(EtCp)2 gas and an O2 gas; and selectively forming a first SiO2-containing insulating film only on a second surface, which is an exposed surface of the insulating film has OH groups, by performing one or more times a process of supplying a TMA gas to the substrate to adsorb TMA only to the second surface and a process of forming an SiO2 film only on a surface of the adsorbed TMA using a silanol group-containing silicon raw material and an oxidizing agent.Type: GrantFiled: September 27, 2018Date of Patent: November 26, 2019Assignee: TOKYO ELECTRON LIMITEDInventors: Yumiko Kawano, Shuji Azumo, Hiroki Murakami, Michitaka Aita, Tadahiro Ishizaka, Koji Akiyama, Yusaku Kashiwagi, Hajime Nakabayashi
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Publication number: 20190355828Abstract: A semiconductor device has an MIS structure that includes a semiconductor layer, a gate insulating film on the semiconductor layer, and a gate electrode on the gate insulating film. The gate insulating film has a layered structure that includes a base SiO2 layer and a high-k layer on the base SiO2 layer and containing Hf. The gate electrode has a portion made of a metal material having a work function of higher than 4.6 eV, the portion being in contact with at least the high-k layer.Type: ApplicationFiled: July 13, 2017Publication date: November 21, 2019Applicant: ROHM CO., LTD.Inventors: Kenji YAMAMOTO, Masatoshi AKETA, Hirokazu ASAHARA, Takashi NAKAMURA, Takuji HOSOI, Heiji WATANABE, Takayoshi SHIMURA, Shuji AZUMO, Yusaku KASHIWAGI
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Patent number: 10453681Abstract: Embodiments of the invention describe methods for selective vertical growth of dielectric material on a dielectric substrate. According to one embodiment, the method includes providing a planarized substrate containing a first material having a recessed feature that is filled with a second material, selectively depositing a graphene layer on the second material relative to the first material, selectively depositing a SiO2 film on the first material relative to the graphene layer, and removing the graphene layer from the substrate. According to one embodiment, the first material includes a dielectric material and the second material includes a metal layer.Type: GrantFiled: April 12, 2018Date of Patent: October 22, 2019Assignee: Tokyo Electron LimitedInventors: Kandabara N. Tapily, Takashi Matsumoto, Yusaku Kashiwagi, Gerrit J. Leusink
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Publication number: 20190096750Abstract: A method of selectively forming a thin film on a substrate to be processed in which a conductive film and an insulating film are exposed to a surface of the substrate includes: selectively forming a first Ru film only on a first surface, which is an exposed surface of the conductive film and formed of one of Ru, RuO2, Pt, Pd, CuO, and CuO2, using an Ru(EtCp)2 gas and an O2 gas; and selectively forming a first SiO2-containing insulating film only on a second surface, which is an exposed surface of the insulating film has OH groups, by performing one or more times a process of supplying a TMA gas to the substrate to adsorb TMA only to the second surface and a process of forming an SiO2 film only on a surface of the adsorbed TMA using a silanol group-containing silicon raw material and an oxidizing agent.Type: ApplicationFiled: September 27, 2018Publication date: March 28, 2019Inventors: Yumiko KAWANO, Shuji AZUMO, Hiroki MURAKAMI, Michitaka AITA, Tadahiro ISHIZAKA, Koji AKIYAMA, Yusaku KASHIWAGI, Hajime NAKABAYASHI
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Publication number: 20180301335Abstract: Embodiments of the invention describe methods for selective vertical growth of dielectric material on a dielectric substrate. According to one embodiment, the method includes providing a planarized substrate containing a first material having a recessed feature that is filled with a second material, selectively depositing a graphene layer on the second material relative to the first material, selectively depositing a SiO2 film on the first material relative to the graphene layer, and removing the graphene layer from the substrate. According to one embodiment, the first material includes a dielectric material and the second material includes a metal layer.Type: ApplicationFiled: April 12, 2018Publication date: October 18, 2018Inventors: Kandabara N. Tapily, Takashi Matsumoto, Yusaku Kashiwagi, Gerrit J. Leusink
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Patent number: 10041174Abstract: A method for forming carbon nanotubes includes preparing a target object having a surface on which one or more openings are formed, each of the openings having a catalyst metal layer on a bottom thereof; performing an oxygen plasma process on the catalyst metal layers; and activating the surfaces of the catalyst metal layers by performing a hydrogen plasma process on the metal catalyst layers subjected to the oxygen plasma process. The method further includes filling carbon nanotubes in the openings on the target object by providing an electrode member having a plurality of through holes above the target object in a processing chamber, and then growing the carbon nanotubes by plasma CVD on the activated catalyst metal layer by diffusing active species in a plasma generated above the electrode member toward the target object through the through holes while applying a DC voltage to the electrode member.Type: GrantFiled: May 29, 2015Date of Patent: August 7, 2018Assignee: TOKYO ELECTRON LIMITEDInventors: Takashi Matsumoto, Masahito Sugiura, Kenjiro Koizumi, Yusaku Kashiwagi
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Patent number: 9293543Abstract: Provided is a method of forming a gate insulating film for use in a MOSFET for a power device. An AlN film is formed on a SiC substrate of a wafer W and then the formation of an AlO film and the formation of an AlN film on the formed AlO film are repeated, thereby forming an AlON film having a laminated structure in which AlO films and AlN films are alternately laminated. A heat treatment is performed on the AlON film having the laminated structure.Type: GrantFiled: October 2, 2013Date of Patent: March 22, 2016Assignees: TOKYO ELECTRON LIMITED, OSAKA UNIVERSITYInventors: Shuji Azumo, Yusaku Kashiwagi, Yuichiro Morozumi, Yu Wamura, Katsushige Harada, Kosuke Takahashi, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi
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Publication number: 20160067680Abstract: A graphene patterning method for forming a graphene of predetermined pattern includes bringing a patterning member in which a catalyst metal layer of the predetermined pattern is formed into contact with a substrate having a graphene oxide film. In bringing the patterning member, the catalyst metal layer is brought into contact with the graphene oxide film.Type: ApplicationFiled: November 12, 2015Publication date: March 10, 2016Inventors: Takashi MATSUMOTO, Yusaku KASHIWAGI
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Patent number: 9219008Abstract: A graphene patterning method for forming a graphene of predetermined pattern includes bringing a patterning member in which a catalyst metal layer of the predetermined pattern is formed into contact with a substrate having a graphene oxide film. In bringing the patterning member, the catalyst metal layer is brought into contact with the graphene oxide film.Type: GrantFiled: January 13, 2014Date of Patent: December 22, 2015Assignee: TOKYO ELECTRON LIMITEDInventors: Takashi Matsumoto, Yusaku Kashiwagi
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Publication number: 20150259801Abstract: A method for forming carbon nanotubes includes preparing a target object having a surface on which one or more openings are formed, each of the openings having a catalyst metal layer on a bottom thereof; performing an oxygen plasma process on the catalyst metal layers; and activating the surfaces of the catalyst metal layers by performing a hydrogen plasma process on the metal catalyst layers subjected to the oxygen plasma process. The method further includes filling carbon nanotubes in the openings on the target object by providing an electrode member having a plurality of through holes above the target object in a processing chamber, and then growing the carbon nanotubes by plasma CVD on the activated catalyst metal layer by diffusing active species in a plasma generated above the electrode member toward the target object through the through holes while applying a DC voltage to the electrode member.Type: ApplicationFiled: May 29, 2015Publication date: September 17, 2015Applicant: TOKYO ELECTRON LIMITEDInventors: Takashi MATSUMOTO, Masahito SUGIURA, Kenjiro KOIZUMI, Yusaku KASHIWAGI
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Publication number: 20150214429Abstract: There is provided a method for manufacturing a rod-type light emitting device, which includes: forming a rod having lateral surfaces and an upper surface on a GaN layer of a first conductivity-type, the rod being made of a GaN of the first conductivity-type; selectively growing a high-resistivity layer on the upper surface of the rod; forming a multi-quantum well layer to cover the lateral surfaces and the upper surface of the rod and the high-resistivity layer; and forming a GaN layer of a second conductivity-type to cover the multi-quantum well layer.Type: ApplicationFiled: January 28, 2015Publication date: July 30, 2015Inventors: Yoji IIZUKA, Yoshihiro KATO, Koji NEISHI, Hitoshi MIURA, Shinya KIKUTA, Yusaku KASHIWAGI, Hiroshi AMANO, Yoshio HONDA
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Publication number: 20150214423Abstract: A method for manufacturing an optical device includes forming a mask on main surface of a first GaN layer such that the mask has one or more openings in first region on the main surface of the first layer, selectively growing first GaN in the opening such that core including the first GaN is formed on exposed portion of the first layer, forming an active layer on the core such that active region is formed, forming a second GaN layer on the active region, removing a portion of the mask covering second region, forming a first electrode in the second region on the first layer, forming a second electrode covering the second layer and extending onto the mask in third region on the first layer, forming a first pad on the first electrode, and forming a second pad in a pad-forming region of the second electrode in the third region.Type: ApplicationFiled: September 10, 2014Publication date: July 30, 2015Applicants: TOKYO ELECTRON LIMITED, NATIONAL UNIVERSITY CORPORATION NAGOYA UNIVERSITYInventors: Shinya KIKUTA, Yoshihiro KATO, Koji NEISHI, Yoji IIZUKA, Hitoshi MIURA, Yusaku KASHIWAGI, Nobuaki TAKAHASHI, Hiroshi AMANO, Yoshio HONDA
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Patent number: 9059178Abstract: A method for forming carbon nanotubes includes preparing a target object having a surface on which one or more openings are formed, each of the openings having a catalyst metal layer on a bottom thereof; performing an oxygen plasma process on the catalyst metal layers; and activating the surfaces of the catalyst metal layers by performing a hydrogen plasma process on the metal catalyst layers subjected to the oxygen plasma process. The method further includes filling carbon nanotubes in the openings on the target object by providing an electrode member having a plurality of through holes above the target object in a processing chamber, and then growing the carbon nanotubes by plasma CVD on the activated catalyst metal layer by diffusing active species in a plasma generated above the electrode member toward the target object through the through holes while applying a DC voltage to the electrode member.Type: GrantFiled: October 31, 2012Date of Patent: June 16, 2015Assignee: TOKYO ELECTRON LIMITEDInventors: Takashi Matsumoto, Masahito Sugiura, Kenjiro Koizumi, Yusaku Kashiwagi
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Publication number: 20150001588Abstract: A trench 107 is coated and sealed with a cap film 111 from above an amorphous or polycrystalline InP film 109A buried in the trench 107. Next, a monocrystalline InP film 109B is formed by monocrystallizing the InP film 109A, with a Si (001) plane of the bottom of the trench 107 as a seed crystal plane, by melting InP by heating a Si wafer W at or above a melting point of InP and then solidifying InP by cooling InP.Type: ApplicationFiled: February 5, 2013Publication date: January 1, 2015Applicant: Tokyo Electron LimitedInventors: Isao Gunji, Yusaku Kashiwagi, Masakazu Sugiyama
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Publication number: 20140199829Abstract: A graphene patterning method for forming a graphene of predetermined pattern includes bringing a patterning member in which a catalyst metal layer of the predetermined pattern is formed into contact with a substrate having a graphene oxide film. In bringing the patterning member, the catalyst metal layer is brought into contact with the graphene oxide film.Type: ApplicationFiled: January 13, 2014Publication date: July 17, 2014Applicant: TOKYO ELECTRON LIMITEDInventors: Takashi MATSUMOTO, Yusaku KASHIWAGI
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Patent number: 8691338Abstract: A first substrate has a source material forming surface on which source materials for forming a polymerized film is formed in a predetermined pattern, and a second substrate has a film forming surface on which the polymerized film will be formed. Here, the first substrate and the second substrate are installed in a processing chamber such that the source material forming surface and the film forming surface face each other. Then, the first substrate is heated to a first temperature at which the source materials on the source material forming surface are evaporated and the second substrate is heated to a second temperature at which the source materials cause polymerization reaction on the film forming surface. Therefore, the polymerized film is formed on the film forming surface by reacting the source materials and evaporated from the first substrate on the film forming surface of the second substrate.Type: GrantFiled: July 17, 2009Date of Patent: April 8, 2014Assignee: Tokyo Electron LimitedInventors: Yumiko Kawano, Yusaku Kashiwagi
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Publication number: 20140094027Abstract: Provided is a method of forming a gate insulating film for use in a MOSFET for a power device. An AlN film is formed on a SiC substrate of a wafer W and then the formation of an AlO film and the formation of an AlN film on the formed AlO film are repeated, thereby forming an AlON film having a laminated structure in which AlO films and AlN films are alternately laminated. A heat treatment is performed on the AlON film having the laminated structure.Type: ApplicationFiled: October 2, 2013Publication date: April 3, 2014Applicants: OSAKA UNIVERSITY, TOKYO ELECTRON LIMITEDInventors: Shuji AZUMO, Yusaku KASHIWAGI, Yuichiro MOROZUMI, Yu WAMURA, Katsushige HARADA, Kosuke TAKAHASHI, Heiji WATANABE, Takayoshi SHIMURA, Takuji HOSOI