Patents by Inventor Yusaku Kiyota

Yusaku Kiyota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190163399
    Abstract: An information processing system and method effectively prevents data loss and the like caused by the duplicate execution of commands. A controller writes a command for a device to a corresponding command queue. The device fetches the command from the corresponding command queue. The command includes a field for storing fetch information which indicates whether the command has been fetched. The device refers to a value of the fetch information of the fetched command. If the value of the fetch information is a first value indicating that the command has not been fetched, the device executes the command after updating the value of the fetch information of the command which is stored in the corresponding command queue to a second value indicating that the command has been fetched. If the value of the fetch information is the second value, the device executes predetermined error processing instead of executing the command.
    Type: Application
    Filed: September 6, 2018
    Publication date: May 30, 2019
    Inventors: Takashi OKADA, Go UEHARA, Yusaku KIYOTA
  • Patent number: 9740404
    Abstract: A control apparatus, which is configured to control a plurality of processors corresponding to a plurality of storage areas arranged at an interface for accessing the storage areas, comprises: an update unit configured to, in a case a command sequence including each command outputted to one of the storage areas is inputted, update, by each one of the processors, a load applied by a command currently being executed to the storage area corresponding to the processor; a selection unit configured to, for one command of the command sequence, based on a load applied by a command currently executed at the processor updated by the update unit, select a processor out of the processors as an allocation destination of the one command; and an output unit configured to output the one command to the processor selected by the selection unit.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: August 22, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Yusaku Kiyota, Tetsuhiro Gotou, Yoshihiro Toyohara
  • Publication number: 20160018989
    Abstract: A control apparatus, which is configured to control a plurality of processors corresponding to a plurality of storage areas arranged at an interface for accessing the storage areas, comprises: an update unit configured to, in a case a command sequence including each command outputted to one of the storage areas is inputted, update, by each one of the processors, a load applied by a command currently being executed to the storage area corresponding to the processor; a selection unit configured to, for one command of the command sequence, based on a load applied by a command currently executed at the processor updated by the update unit, select a processor out of the processors as an allocation destination of the one command; and an output unit configured to output the one command to the processor selected by the selection unit.
    Type: Application
    Filed: May 31, 2013
    Publication date: January 21, 2016
    Inventors: Yusaku KIYOTA, Tetsuhiro GOTOU, Yoshihiro TOYOHARA
  • Publication number: 20140136740
    Abstract: An input-output control unit includes: an interface control circuit for controlling data on a frame basis with respect to each of transmitted and received frames; a reception buffer control circuit for transferring receive-data stored in a receive-data buffer to a command issuer; a transmission buffer control circuit for transferring send-data stored in a send-data buffer to an interface; a plurality of protocol control circuits for controlling transfer of the receive-data and the send-data; and a received frame routing control circuit for selecting a location to which the received frame should be assigned, from among the plurality of protocol control circuits, based on control information attached to the received frame received by the interface control circuit and assigning processing on the received frame to the selected protocol control circuit.
    Type: Application
    Filed: June 29, 2011
    Publication date: May 15, 2014
    Applicant: Hitachi, Ltd.
    Inventors: Hideaki Monji, Yusaku Kiyota