Abstract: A computer arrangement for facilitating the sharing of information among computers at a memory level. Each computer includes means for accessing the main memory of another computer of the complex at machine word level, means for transmitting an interruption instruction from itself to the arithmetic control unit of the other computer, means for detecting a problem in the arithmetic control unit of itself, and means for altering one section of the logic address viewed from itself to some of a plurality of physical address spaces such as to make the same the logic address of a shared information storage region of the computer complex viewed from the program of each of the member computers. Shared information required for each computer is stored in its own main memory. When a problem occurs in the computer having the aforesaid shared information storage region it becomes evident in the computer's arithmetic control unit. As a result, an interruption instruction is sent to each of the other computers.

Abstract: A data processor having a stack area with a desirable variable size formed on a desirable area of a main memory unit in accordance with a direction by a user program, is provided with a stack control register group for controlling the stack area. A stack upper address register in the stack control register group holds the upper address specified on the stack area. The stack lower address register holds the lower limit address specified. A control stack pointer register holds the start address of a control stack area formed on the stack area for storing the number of a register specified by a user program and the contents thereof. A data stack pointer register holds the start address of the data stack area which is formed on said stack area and used by the user program.