Patents by Inventor Yusaku Ono
Yusaku Ono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8719740Abstract: An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area (114) for forming a logic circuit includes a first area (114b, 170) which is subjected to optical proximity correction with predetermined accuracy, and a second area (114a, 180) which is subjected to optical proximity correction with accuracy lower than said predetermined accuracy. Especially, the first area (114b, 170) includes a gate interconnection line (172) which acts as a transistor, and the second area (114a, 180) includes a dummy layout pattern (182) which does not act as a transistor.Type: GrantFiled: May 6, 2013Date of Patent: May 6, 2014Assignee: Renesas Electronics CorporationInventors: Hironobu Taoka, Yusaku Ono
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Publication number: 20130249597Abstract: An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area (114) for forming a logic circuit includes a first area (114b, 170) which is subjected to optical proximity correction with predetermined accuracy, and a second area (114a, 180) which is subjected to optical proximity correction with accuracy lower than said predetermined accuracy. Especially, the first area (114b, 170) includes a gate interconnection line (172) which acts as a transistor, and the second area (114a, 180) includes a dummy layout pattern (182) which does not act as a transistor.Type: ApplicationFiled: May 6, 2013Publication date: September 26, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hironobu TAOKA, Yusaku ONO
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Patent number: 8458627Abstract: An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area (114) for forming a logic circuit includes a first area (114b, 170) which is subjected to optical proximity correction with predetermined accuracy, and a second area (114a, 180) which is subjected to optical proximity correction with accuracy lower than said predetermined accuracy. Especially, the first area (114b, 170) includes a gate interconnection line (172) which acts as a transistor, and the second area (114a, 180) includes a dummy layout pattern (182) which does not act as a transistor.Type: GrantFiled: December 21, 2011Date of Patent: June 4, 2013Assignee: Renesas Electronics CorporationInventors: Hironobu Taoka, Yusaku Ono
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Publication number: 20120091510Abstract: An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area (114) for forming a logic circuit includes a first area (114b, 170) which is subjected to optical proximity correction with predetermined accuracy, and a second area (114a, 180) which is subjected to optical proximity correction with accuracy lower than said predetermined accuracy. Especially, the first area (114b, 170) includes a gate interconnection line (172) which acts as a transistor, and the second area (114a, 180) includes a dummy layout pattern (182) which does not act as a transistor.Type: ApplicationFiled: December 21, 2011Publication date: April 19, 2012Applicant: Renesas Electronics CorporationInventors: Hironobu TAOKA, Yusaku Ono
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Patent number: 8103977Abstract: An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area (114) for forming a logic circuit includes a first area (114b, 170) which is subjected to optical proximity correction with predetermined accuracy, and a second area (114a, 180) which is subjected to optical proximity correction with accuracy lower than said predetermined accuracy. Especially, the first area (114b, 170) includes a gate interconnection line (172) which acts as a transistor, and the second area (114a, 180) includes a dummy layout pattern (182) which does not act as a transistor.Type: GrantFiled: April 25, 2006Date of Patent: January 24, 2012Assignee: Renesas Electronics CorporationInventors: Hironobu Taoka, Yusaku Ono
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Patent number: 7844934Abstract: According to the present invention, a method for designing a semiconductor integrated circuit layout comprises the steps of: arranging basic logic cells which are circuit patterns corresponding to logic components of a semiconductor integrated circuit; arranging wiring between the basic logic cells; searching for a blank area in which none of the basic logic cells is arranged; extracting a rectangular region from the blank area; if the rectangular region is larger than a specified size, arranging fill cells in the rectangular region according to a predetermined rule and grouping the fill cells into pseudo-hierarchical cells according to a predetermined rule to form a hierarchy; arranging fill cells in the remaining blank areas; and performing optical proximity effect correction on the semiconductor integrated circuit pattern.Type: GrantFiled: July 14, 2006Date of Patent: November 30, 2010Assignees: Renesas Electronics Corporation, Panasonic Corporation, Fujitsu Microelectronics Limited, Kabushiki Kaisha ToshibaInventors: Yusaku Ono, Osamu Suga, Kazuyuki Sakata, Hirofumi Taguchi, Yushi Okuno, Toshiaki Sugioka, Daisuke Kondo
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Publication number: 20090278569Abstract: An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area (114) for forming a logic circuit includes a first area (114b, 170) which is subjected to optical proximity correction with predetermined accuracy, and a second area (114a, 180) which is subjected to optical proximity correction with accuracy lower than said predetermined accuracy. Especially, the first area (114b, 170) includes a gate interconnection line (172) which acts as a transistor, and the second area (114a, 180) includes a dummy layout pattern (182) which does not act as a transistor.Type: ApplicationFiled: April 25, 2006Publication date: November 12, 2009Inventors: Hironobu Taoka, Yusaku Ono
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Publication number: 20070124714Abstract: According to the present invention, a method for designing a semiconductor integrated circuit layout comprises the steps of: arranging basic logic cells which are circuit patterns corresponding to logic components of a semiconductor integrated circuit; arranging wiring between the basic logic cells; searching for a blank area in which none of the basic logic cells is arranged; extracting a rectangular region from the blank area; if the rectangular region is larger than a specified size, arranging fill cells in the rectangular region according to a predetermined rule and grouping the fill cells into pseudo-hierarchical cells according to a predetermined rule to form a hierarchy; arranging fill cells in the remaining blank areas; and performing optical proximity effect correction on the semiconductor integrated circuit pattern.Type: ApplicationFiled: July 14, 2006Publication date: May 31, 2007Applicants: Renesas Technology Corp., Matsushita Electric Industrial Co., Ltd., NEC Electronics Corporation, Fujitsu Limited, Kabushiki Kaisha ToshibaInventors: Yusaku Ono, Osamu Suga, Kazuyuki Sakata, Hirofumi Taguchi, Yushi Okuno, Toshiaki Sugioka, Daisuke Kondo
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Patent number: 6848096Abstract: An apparatus for correcting layout pattern data composed of a computer system includes eight sections. The first section holds the layout pattern data. The second section holds correcting requirements. The third section extracts and divides correction target edges of the layout pattern. The fourth section sets a permissible correction range. The fifth section extracts insufficient process margin parts. The sixth section resets the permissible correction range. The seventh section performs correction by simulation. The eighth section holds finished correction layout pattern data. By simulation, the apparatus predicts finished layout patterns at high rate and high precision within the movable range of the correction target edges which can secure process margins.Type: GrantFiled: April 29, 2003Date of Patent: January 25, 2005Assignee: Renesas Technology Corp.Inventor: Yusaku Ono
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Patent number: 6687885Abstract: A layout pattern data correction device includes: (a) edge extracting means for extracting a first target edge to be corrected from an original layout pattern of a circuit; (b) edge modifying region setting means for setting an edge modifying region in which the first target edge is modified with a predetermined point in the first target edge taken as a center; (c) edge modifying means for modifying the first target edge within the edge modifying region into a second target edge to be corrected; (d) corrected pattern forming means for forming a corrected pattern based on the second target edge; and (e) boolean operation means for performing a predetermined boolean operation based on both of the original layout pattern and the corrected pattern.Type: GrantFiled: February 27, 2001Date of Patent: February 3, 2004Assignee: Renesas Technology Corp.Inventor: Yusaku Ono
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Publication number: 20030208741Abstract: An apparatus for correcting layout pattern data composed of a computer system includes eight sections. The first section holds the layout pattern data. The second section holds correcting requirements. The third section extracts and divides correction target edges of the layout pattern. The fourth section sets a permissible correction range. The fifth section extracts insufficient process margin parts. The sixth section resets the permissible correction range. The seventh section performs correction by simulation. The eighth section holds finished correction layout pattern data. By simulation, the apparatus predicts finished layout patterns at high rate and high precision within the movable range of the correction target edges which can secure process margins.Type: ApplicationFiled: April 29, 2003Publication date: November 6, 2003Applicant: RENESAS TECHNOLOGY CORP.Inventor: Yusaku Ono
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Patent number: 6536015Abstract: The invention provides an apparatus and a method of correcting layout pattern. The apparatus has a deletion region side extracting section for extracting sides of a region to be deleted having a predetermined shape such as protrusion, notch or step in a layout pattern of a circuit, a deletion-use pattern generator for generating a deletion-use pattern based on the extracted sides, and an operating section for executing a predetermined operation to the layout pattern with the deletion-use pattern so as to remove the region to be deleted from the original layout pattern.Type: GrantFiled: March 19, 2001Date of Patent: March 18, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Yusaku Ono
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Publication number: 20020026624Abstract: A layout pattern data correction device includes: (a) edge extracting means for extracting a first target edge to be corrected from an original layout pattern of a circuit; (b) edge modifying region setting means for setting an edge modifying region in which the first target edge is modified with a predetermined point in the first target edge taken as a center; (c) edge modifying means for modifying the first target edge within the edge modifying region into a second target edge to be corrected; (d) corrected pattern forming means for forming a corrected pattern based on the second target edge; and (e) boolean operation means for performing a predetermined boolean operation based on both of the original layout pattern and the corrected pattern.Type: ApplicationFiled: February 27, 2001Publication date: February 28, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Yusaku Ono
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Publication number: 20020007481Abstract: The invention provides an apparatus and a method of correcting layout pattern. The apparatus has a deletion region side extracting section for extracting sides of a region to be deleted having a predetermined shape such as protrusion, notch or step in a layout pattern of a circuit, a deletion-use pattern generator for generating a deletion-use pattern based on the extracted sides, and an operating section for executing a predetermined operation to the layout pattern with the deletion-use pattern so as to remove the region to be deleted from the original layout pattern.Type: ApplicationFiled: March 19, 2001Publication date: January 17, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Yusaku Ono
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Patent number: 6298473Abstract: A correction target edge extracting part of a layout pattern data correction apparatus extracts a correction target edge from circuit layout patterns. A density calculation region setting part of the apparatus sets density calculation regions around the center of the correction target edge. An area density calculating part calculates an area density of design patterns within the density calculation regions. Given the area density thus calculated, a correction pattern size calculating part calculates the size of a correction pattern to be superposed on the correction target edge. In accordance with the calculated size, a correction pattern generating part generates the correction pattern. A graphic calculating part adds up the correction pattern and design layout patterns to generate corrected layout patterns.Type: GrantFiled: December 3, 1998Date of Patent: October 2, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yusaku Ono, Koichi Moriizumi