Abstract: A semiconductor chip for correcting an aligned error comprises a memory array; a transceiver circuit; and an Error Correction Code (ECC) circuit, wherein the ECC circuit is configured to: receive target data to be encoded, encode the target data by multiplying a generator matrix of a previously generated ECC by the target data, store the encoded target data in the memory array, check a data transformed from the encoded target data, and generate an error corrected data by correcting only a single error of the transformed data and an adjacent error that does not exceed a first value boundary of a predetermined number of bits by using a parity check matrix of the ECC, and output the error corrected data.