Patents by Inventor Yushi Hu
Yushi Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11462474Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a substrate, a plurality of NAND strings on the substrate, one or more peripheral devices above the NAND strings, a single crystalline silicon layer above the peripheral devices, and one or more interconnect layers between the peripheral devices and the NAND strings. In some embodiments, the NAND memory device includes a bonding interface at which an array interconnect layer contacts a peripheral interconnect layer.Type: GrantFiled: April 17, 2019Date of Patent: October 4, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Jifeng Zhu, Zhenyu Lu, Jun Chen, Yushi Hu, Qian Tao, Simon Shi-Ning Yang, Steve Weiyi Yang
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Publication number: 20220238543Abstract: The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.Type: ApplicationFiled: April 19, 2022Publication date: July 28, 2022Inventors: Luan C. Tran, Hongbin Zhu, John D. Hopkins, Yushi Hu
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Publication number: 20220238556Abstract: Embodiments of a channel hole plug structure of 3D memory devices and fabricating methods thereof are disclosed. The memory device includes an alternating layer stack disposed on a substrate, an insulating layer disposed on the alternating dielectric stack, a channel hole extending vertically through the alternating dielectric stack and the insulating layer, a channel structure including a channel layer in the channel hole, and a channel hole plug in the insulating layer and above the channel structure. The channel hole plug is electrically connected with the channel layer. A projection of the channel hole plug in a lateral plane covers a projection of the channel hole in the lateral plane.Type: ApplicationFiled: April 19, 2022Publication date: July 28, 2022Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Li Hong Xiao, Zhenyu Lu, Qian Tao, Yushi Hu, Jun Chen, LongDong Liu, Meng Wang
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Patent number: 11380701Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.Type: GrantFiled: December 17, 2020Date of Patent: July 5, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Yue Qiang Pu, Jin Wen Dong, Jun Chen, Zhenyu Lu, Qian Tao, Yushi Hu, Zhao Hui Tang, Li Hong Xiao, Yu Ting Zhou, Sizhe Li, Zhaosong Li
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Patent number: 11329061Abstract: A method for forming a three-dimensional memory device includes disposing a material layer over a substrate, forming a plurality of channel-forming holes and a plurality of sacrificial holes around the plurality of channel-forming holes in an array-forming region of the material layer, and forming a plurality of semiconductor channels based on the channel-forming holes and at least one gate line slit (GLS) based on at least one of the plurality of sacrificial holes. A location of the at least one GLS overlaps with the at least one of the plurality of sacrificial holes.Type: GrantFiled: September 10, 2018Date of Patent: May 10, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Li Hong Xiao, Qian Tao, Yushi Hu, Xiao Tian Cheng, Jian Xu, Haohao Yang, Yue Qiang Pu, Jin Wen Dong
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Patent number: 11315941Abstract: The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.Type: GrantFiled: March 4, 2019Date of Patent: April 26, 2022Assignee: Micron Technology, Inc.Inventors: Luan C. Tran, Hongbin Zhu, John D. Hopkins, Yushi Hu
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Patent number: 11309327Abstract: Embodiments of a channel hole plug structure of 3D memory devices and fabricating methods thereof are disclosed. The memory device includes an alternating layer stack disposed on a substrate, an insulating layer disposed on the alternating dielectric stack, a channel hole extending vertically through the alternating dielectric stack and the insulating layer, a channel structure including a channel layer in the channel hole, and a channel hole plug in the insulating layer and above the channel structure. The channel hole plug is electrically connected with the channel layer. A projection of the channel hole plug in a lateral plane covers a projection of the channel hole in the lateral plane.Type: GrantFiled: July 26, 2018Date of Patent: April 19, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Li Hong Xiao, Zhenyu Lu, Qian Tao, Yushi Hu, Jun Chen, LongDong Liu, Meng Wang
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Patent number: 11289511Abstract: Embodiments of ferroelectric memory devices and methods for forming the ferroelectric memory devices are disclosed. In an example, a ferroelectric memory cell includes a first electrode, a second electrode, a ferroelectric layer disposed between the first electrode and the second electrode, and a recess between a side surface of at least one of the first electrode or the second electrode and a side surface of the ferroelectric layer.Type: GrantFiled: July 2, 2020Date of Patent: March 29, 2022Assignee: WUXI PETABYTE TECHNOLOGIES CO, LTD.Inventor: Yushi Hu
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Patent number: 11271004Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.Type: GrantFiled: December 14, 2020Date of Patent: March 8, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Yue Qiang Pu, Jin Wen Dong, Jun Chen, Zhenyu Lu, Qian Tao, Yushi Hu, Zhao Hui Tang, Li Hong Xiao, Yu Ting Zhou, Sizhe Li, Zhaosong Li
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Patent number: 11264397Abstract: Embodiments of source structure of a three-dimensional (3D) memory device and method for forming the source structure of the 3D memory device are disclosed. In an example, a NAND memory device includes a substrate, an alternating conductor/dielectric stack, a NAND string, a source conductor layer, and a source contact. The alternating conductor/dielectric stack includes a plurality of conductor/dielectric pairs above the substrate. The NAND string extends vertically through the alternating conductor/dielectric stack. The source conductor layer is above the alternating conductor/dielectric stack and is in contact with an end of the NAND string. The source contact includes an end in contact with the source conductor layer. The NAND string is electrically connected to the source contact by the source conductor layer. In some embodiments, the source conductor layer includes one or more conduction regions each including one or more of a metal, a metal alloy, and a metal silicide.Type: GrantFiled: September 21, 2020Date of Patent: March 1, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Yushi Hu, Zhenyu Lu, Qian Tao, Jun Chen, Simon Shi-Ning Yang, Steve Weiyi Yang
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Publication number: 20220005829Abstract: Embodiments of ferroelectric memory devices and methods for forming the ferroelectric memory devices are disclosed. In an example, a ferroelectric memory cell includes a first electrode, a second electrode, a ferroelectric layer disposed between the first electrode and the second electrode, and a recess between a side surface of at least one of the first electrode or the second electrode and a side surface of the ferroelectric layer.Type: ApplicationFiled: July 2, 2020Publication date: January 6, 2022Inventor: Yushi Hu
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Publication number: 20210408026Abstract: Aspects of the disclosure provide a method for fabricating semiconductor device. The method includes characterizing an etch process that is used to etch channel holes and dummy channel holes in a stack of alternating sacrificial gate layers and insulating layers upon a substrate of a semiconductor device. The channel holes are in a core region and the dummy channel holes are in a staircase region. The stack of alternating sacrificial gate layers and insulating layers extend from the core region into in the staircase region of a stair-step form. The method further includes determining a first shape for defining the dummy channel holes in a layout based on the characterization of the etch process. The first shape is different from a second shape for defining the channel holes.Type: ApplicationFiled: September 7, 2021Publication date: December 30, 2021Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Miao SHEN, Li Hong XIAO, Yushi HU, Qian TAO, Mei Lan GUO, Yong ZHANG, Jian Hua SUN
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Patent number: 11211393Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.Type: GrantFiled: December 8, 2020Date of Patent: December 28, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Yue Qiang Pu, Jin Wen Dong, Jun Chen, Zhenyu Lu, Qian Tao, Yushi Hu, Zhao Hui Tang, Li Hong Xiao, Yu Ting Zhou, Sizhe Li, Zhaosong Li
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Patent number: 11211397Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a substrate, one or more peripheral devices on the substrate, a plurality of NAND strings above the peripheral devices, a single crystalline silicon layer above and in contact with the NAND strings, and interconnect layers formed between the peripheral devices and the NAND strings. In some embodiments, the NAND memory device includes a bonding interface at which an array interconnect layer contacts a peripheral interconnect layer.Type: GrantFiled: July 27, 2018Date of Patent: December 28, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Jun Chen, Jifeng Zhu, Yushi Hu, Qian Tao, Simon Shi-Ning Yang, Steve Weiyi Yang
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Publication number: 20210399001Abstract: Various embodiments disclose a 3D memory device, including a substrate; a plurality of conductor layers disposed on the substrate; a plurality of NAND strings disposed on the substrate; and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction.Type: ApplicationFiled: September 2, 2021Publication date: December 23, 2021Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Xiaowang DAI, Zhenyu LU, Jun CHEN, Qian TAO, Yushi HU, Jifeng ZHU, Jin Wen DONG, Ji XIA, Zhong ZHANG, Yan Ni LI
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Publication number: 20210398999Abstract: Aspects of the disclosure provide methods for manufacturing semiconductor devices. One of the methods forms a string of transistors in a semiconductor device over a substrate of the semiconductor device. The method includes forming a first substring of transistors having a first channel structure that includes a first channel layer and a first gate dielectric structure that extend along a vertical direction over the substrate. The method includes forming a channel connector over the first substring and forming the second substring above the channel connector. The second substring has a second channel structure. The second channel structure includes the second channel layer and a second gate dielectric structure that extend along the vertical direction. The second gate dielectric structure is formed above the channel connector. The channel connector electrically couples the first channel layer and the second channel layer.Type: ApplicationFiled: August 31, 2021Publication date: December 23, 2021Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Ruo Fang ZHANG, Enbo Wang, Haohao Yang, Qianbing Xu, Yushi Hu, Qian Tao
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Publication number: 20210391347Abstract: In a three-dimensional memory device, an interconnect structure is formed over a substrate and a first deck is formed over the interconnect structure. The first deck includes alternating first insulating layers and first word line layers, and a first channel structure extending through the first stack. The first channel structure has a first channel dielectric region and a first channel layer. The first channel dielectric region is formed along sidewalls of the first channel structure, positioned over a top surface of the interconnect structure, and in contact with the first insulating layers and the first word line layers. The first channel layer is formed along the first channel dielectric region, and includes a rounded projection that extends away from the top surface of the interconnect structure, extends outwards into the first stack at an interface of the interconnect structure, the first channel structure and the first stack.Type: ApplicationFiled: August 26, 2021Publication date: December 16, 2021Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Ruo Fang ZHANG, Enbo WANG, Haohao YANG, Qianbing XU, Yushi HU, Fushan ZHANG
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Patent number: 11201164Abstract: Some embodiments include a NAND memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels, and is spaced from the control gate regions by charge-blocking material. The charge-trapping material along vertically adjacent wordline levels is spaced by intervening regions through which charge migration is impeded. Channel material extends vertically along the stack and is spaced from the charge-trapping material by charge-tunneling material. Some embodiments include methods of forming NAND memory arrays.Type: GrantFiled: August 21, 2019Date of Patent: December 14, 2021Assignee: Micron Technology, Inc.Inventors: Akira Goda, Yushi Hu
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Publication number: 20210343743Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.Type: ApplicationFiled: July 18, 2021Publication date: November 4, 2021Applicant: Micron Technology, Inc.Inventors: Justin B. Dorhout, David Daycock, Kunal R. Parekh, Martin C. Roberts, Yushi Hu
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Patent number: 11145667Abstract: In a memory device, a lower memory cell string is formed over a substrate to include a first channel structure, a plurality of first word line layers and first insulating layers. The first channel structure protrudes from the substrate and passes through the first word line layers and first insulating layers. An inter deck contact is formed over the lower memory cell string and connected with the first channel structure. An upper memory cell string is formed over the inter deck contact. The upper memory cell string includes a second channel structure, a plurality of second word lines and second insulating layers. The second channel structure passes through the second word lines and second insulating layers, and extends to the inter deck contact, and further extends laterally into the second insulating layers. A channel dielectric region of the second channel structure is above the inter deck contact.Type: GrantFiled: March 28, 2019Date of Patent: October 12, 2021Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Ruo Fang Zhang, Enbo Wang, Haohao Yang, Qianbing Xu, Yushi Hu, Fushan Zhang