Patents by Inventor Yuso Udo

Yuso Udo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7700381
    Abstract: A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products.
    Type: Grant
    Filed: February 9, 2006
    Date of Patent: April 20, 2010
    Assignee: Kabushikia Kaisha Toshiba
    Inventors: Tsunetoshi Arikado, Masao Iwase, Soichi Nadahara, Yuso Udo, Yukihiro Ushiku, Shinichi Nitta, Moriya Miyashita, Junji Sugamoto, Hiroaki Yamada, Hajime Nagano, Katsujiro Tanzawa, Hiroshi Matsushita, Norihiko Tsuchiya, Katsuya Okumura
  • Patent number: 7420249
    Abstract: A semiconductor device including a first semiconductor layer formed on a semiconductor substrate, a second semiconductor layer surrounding the first semiconductor layer, the second semiconductor layer being formed on the semiconductor substrate with one of an insulating film and a cavity, and a third semiconductor layer surrounding the second semiconductor layer, the third semiconductor layer being formed on the semiconductor substrate.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: September 2, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Sato, Hajime Nagano, Ichiro Mizushima, Takashi Yamada, Yuso Udo, Shinichi Nitta
  • Publication number: 20080012078
    Abstract: A semiconductor device including a first semiconductor layer formed on a semiconductor substrate, a second semiconductor layer surrounding the first semiconductor layer, the second semiconductor layer being formed on the semiconductor substrate with one of an insulating film and a cavity, and a third semiconductor layer surrounding the second semiconductor layer, the third semiconductor layer being formed on the semiconductor substrate.
    Type: Application
    Filed: September 4, 2007
    Publication date: January 17, 2008
    Inventors: Tsutomu Sato, Hajime Nagano, Ichiro Mizushima, Takashi Yamada, Yuso Udo, Shinichi Nitta
  • Publication number: 20060131696
    Abstract: A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products.
    Type: Application
    Filed: February 9, 2006
    Publication date: June 22, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tsunetoshi Arikado, Masao Iwase, Soichi Nadahara, Yuso Udo, Yukihiro Ushiku, Shinichi Nitta, Moriya Miyashita, Junji Sugamoto, Hiroaki Yamada, Hajime Nagano, Katsujiro Tanzawa, Hiroshi Matsushita, Norihiko Tsuchiya, Katsuya Okumura
  • Patent number: 7057259
    Abstract: A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: June 6, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsunetoshi Arikado, Masao Iwase, Soichi Nadahara, Yuso Udo, Yukihiro Ushiku, Shinichi Nitta, Moriya Miyashita, Junji Sugamoto, Hiroaki Yamada, Hajime Nagano, Katsujiro Tanzawa, Hiroshi Matsushita, Norihiko Tsuchiya, Katsuya Okumura
  • Patent number: 7019365
    Abstract: A semiconductor device according to an aspect of the present invention comprises a first semiconductor layer and a plurality of second semiconductor layers. The first semiconductor layer is formed in a first region of a semiconductor substrate with one of an insulating film and a cavity interposed between the semiconductor substrate and the first semiconductor layer. The plurality of second semiconductor layers is formed in second regions of the semiconductor substrate.
    Type: Grant
    Filed: August 11, 2003
    Date of Patent: March 28, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Sato, Hajime Nagano, Ichiro Mizushima, Takashi Yamada, Yuso Udo, Shinichi Nitta
  • Publication number: 20050156245
    Abstract: A semiconductor device according to an aspect of the present invention comprises a first semiconductor layer and a plurality of second semiconductor layers. The first semiconductor layer is formed in a first region of a semiconductor substrate with one of an insulating film and a cavity interposed between the semiconductor substrate and the first semiconductor layer. The plurality of second semiconductor layers is formed in second regions of the semiconductor substrate.
    Type: Application
    Filed: March 8, 2005
    Publication date: July 21, 2005
    Inventors: Tsutomu Sato, Hajime Nagano, Ichiro Mizushima, Takashi Yamada, Yuso Udo, Shinichi Nitta
  • Publication number: 20040026739
    Abstract: A semiconductor device according to an aspect of the present invention comprises a first semiconductor layer and a plurality of second semiconductor layers. The first semiconductor layer is formed in a first region of a semiconductor substrate with one of an insulating film and a cavity interposed between the semiconductor substrate and the first semiconductor layer. The plurality of second semiconductor layers is formed in second regions of the semiconductor substrate.
    Type: Application
    Filed: August 11, 2003
    Publication date: February 12, 2004
    Inventors: Tsutomu Sato, Hajime Nagano, Ichiro Mizushima, Takashi Yamada, Yuso Udo, Shinichi Nitta
  • Patent number: 6630714
    Abstract: A semiconductor device according to an aspect of the present invention comprises a first semiconductor layer and a plurality of second semiconductor layers. The first semiconductor layer is formed in a first region of a semiconductor substrate with one of an insulating film and a cavity interposed between the semiconductor substrate and the first semiconductor layer. The plurality of second semiconductor layers is formed in second regions of the semiconductor substrate.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: October 7, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Sato, Hajime Nagano, Ichiro Mizushima, Takashi Yamada, Yuso Udo, Shinichi Nitta
  • Publication number: 20030122191
    Abstract: A semiconductor device according to an aspect of the present invention comprises a first semiconductor layer and a plurality of second semiconductor layers. The first semiconductor layer is formed in a first region of a semiconductor substrate with one of an insulating film and a cavity interposed between the semiconductor substrate and the first semiconductor layer. The plurality of second semiconductor layers is formed in second regions of the semiconductor substrate.
    Type: Application
    Filed: March 7, 2002
    Publication date: July 3, 2003
    Inventors: Hajime Nagano, Ichiro Mizushima, Takashi Yamada, Yuso Udo, Shinichi Nitta
  • Patent number: 6515733
    Abstract: A semiconductor wafer having an effective chip region set within an effective element region in which an element is formed and required for forming a single chip and an ineffective chip region which includes an ineffective element region in which no element is formed and required for forming a single chip. A degree of unevenness of a surface of the semiconductor wafer is measured at a plurality of sites within a predetermined region by an unevenness measuring section by applying light thereof, so that unevenness data are output. The predetermined region includes either or a part of both of the effective chip region and the ineffective chip region. A reference plane to which light is applied is determined by using only unevenness data of the effective chip region after unevenness data of the ineffective chip region are eliminated from the unevenness data.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: February 4, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yuso Udo
  • Publication number: 20030003608
    Abstract: A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products.
    Type: Application
    Filed: March 20, 2002
    Publication date: January 2, 2003
    Inventors: Tsunetoshi Arikado, Masao Iwase, Soichi Nadahara, Yuso Udo, Yukihiro Ushiku, Shinichi Nitta, Moriya Miyashita, Junji Sugamoto, Hiroaki Yamada, Hajime Nagano, Katsujiro Tanzawa, Hiroshi Matsushita, Norihiko Tsuchiya, Katsuya Okumura