Abstract: A method for speeding the re-use of Physical Register Names (PRNs), and hence the processor registers, in a processor. The method involves returning a PRN to a freelist for reuse when it is obsolete even when it is not complete, and blocking writes to the Processor Register File (PRF) by obsolete realms.

Abstract: In certain aspects of the disclosure, an apparatus comprises a first scheduling pool associated with a first minimum scheduling latency and a second scheduling pool associated with a second minimum scheduling latency, the second minimum scheduling latency greater than the first minimum scheduling latency. A common instruction picker is coupled to both the first scheduling pool and the second scheduling pool. The common instruction picker may be configured to select a first instruction from the first scheduling pool and a second instruction from the second scheduling pool, and then choose either the first instruction or second instruction for dispatch according to a picking policy.

Abstract: Providing early pipeline optimization of conditional instructions in processor-based systems is disclosed. In one aspect, an instruction pipeline of a processor-based system detects a mispredicted branch (i.e., following a misprediction of a condition associated with a speculatively executed conditional branch instruction), and records a current state of one or more condition flags as a condition flags snapshot. After a pipeline flush is initiated and a corrected fetch path is restarted, an instruction decode stage of the instruction pipeline uses the condition flags snapshot to apply optimizations to conditional instructions detected within the corrected fetch path. According to some aspects, the condition flags snapshot is subsequently invalidated upon encountering a condition-flag-writing instruction within the corrected fetch path.

Abstract: A method for speeding the re-use of Physical Register Names (PRNs), and hence the processor registers, in a processor. The method involves returning a PRN to a freelist for reuse when it is obsolete even when it is not complete, and blocking writes to the Processor Register File (PRF) by obsolete realms.

Abstract: A load instruction, for loading a register among a set of registers, is scheduled. Associated with scheduling the load instruction, a register dependency vector, corresponding to the register, is set to a state identifying the load instruction. A consumer instruction is scheduled, having a set of operand register and a target register, the register being in the set of operand registers. A target register dependency vector, corresponding to the target register is set in the memory. Based at least in part on the register being in the set of operand registers, a value of the target register dependency vector identifies the load instruction. Optionally, upon receiving a cache miss notice associated with the load instruction, the target register dependency vector is retrieved.

Abstract: Systems and methods of handling a register file include, in a first instruction set architecture (ISA) mode assigning a first subset of tracking resources to logical registers of a first logical register subset for tracking mappings to full granularity and first lower granularity physical registers of a first physical register subset, and assigning a second subset of tracking resources to logical registers of a second logical register subset for tracking mappings to second lower granularity physical registers of the first physical register subset. The second subset of tracking resources are configured for tracking at least the logical registers of the second logical register subset mappings to physical registers of a second physical register subset in a second ISA mode, wherein the second physical register subset is available to the second ISA mode but not the first ISA mode.

Abstract: Apparatus and methods provide early access of instructions. A fetch queue is coupled to an instruction cache and configured to store a mix of processor instructions for a first processor and coprocessor instructions for a second processor. A coprocessor instruction selector is coupled to the fetch queue and configured to copy coprocessor instructions from the fetch queue. A queue is coupled to the coprocessor instruction selector and from which coprocessor instructions are accessed for execution before the coprocessor instruction is issued to the first processor. Execution of the copied coprocessor instruction is started in the coprocessor before the coprocessor instruction is issued to a processor. The execution of the copied coprocessor instruction is completed based on information received from the processor after the coprocessor instruction has been issued to the processor.

Abstract: A queuing apparatus having a hierarchy of queues, in one of a number of aspects, is configured to control backpressure between processors in a multiprocessor system. A fetch queue is coupled to an instruction cache and configured to store first instructions for a first processor and second instructions for a second processor in an order fetched from the instruction cache. An in-order queue is coupled to the fetch queue and configured to store the second instructions accepted from the fetch queue in response to a write indication. An out-of-order queue is coupled to the fetch queue and to the in-order queue and configured to store the second instructions accepted from the fetch queue in response to an indication that space is available in the out-of-order queue, wherein the second instructions may be accessed out-of-order with respect to other second instructions executing on different execution pipelines.

Abstract: Systems and methods for tracking data hazards in a processor. The processor comprises a pipelined architecture configured to execute a first instruction and a second instruction, wherein the second instruction is older than the first instruction. At least one of the first and second instructions comprises at least one operand expressed as a range of registers. Hazard detection logic is configured to compare the first instruction and the second instruction to determine if there is a data hazard, prior to expanding the second instruction.

Abstract: A queuing apparatus having a hierarchy of queues, in one of a number of aspects, is configured to control backpressure between processors in a multiprocessor system. A fetch queue is coupled to an instruction cache and configured to store first instructions for a first processor and second instructions for a second processor in an order fetched from the instruction cache. An in-order queue is coupled to the fetch queue and configured to store the second instructions accepted from the fetch queue in response to a write indication. An out-of-order queue is coupled to the fetch queue and to the in-order queue and configured to store the second instructions accepted from the fetch queue in response to an indication that space is available in the out-of-order queue, wherein the second instructions may be accessed out-of-order with respect to other second instructions executing on different execution pipelines.

Abstract: Methods and apparatus for processing instructions by elaboration of instructions prior to issuing the instructions for execution are described. An instruction is received at a hybrid instruction queue comprised of a first queue and a second queue. When the second queue has available space, the instruction is elaborated to expand one or more bit fields to reduce decoding complexity when the elaborated instruction is issued, wherein the elaborated instruction is stored in the second queue. When the second queue does not have available space, the instruction is stored in an unelaborated form in a first queue. The first queue is configured as an exemplary in-order queue and the second queue is configured as an exemplary out-of-order queue.

Abstract: Apparatus and methods provide early access of instructions. A fetch queue is coupled to an instruction cache and configured to store a mix of processor instructions for a first processor and coprocessor instructions for a second processor. A coprocessor instruction selector is coupled to the fetch queue and configured to copy coprocessor instructions from the fetch queue. A queue is coupled to the coprocessor instruction selector and from which coprocessor instructions are accessed for execution before the coprocessor instruction is issued to the first processor. Execution of the copied coprocessor instruction is started in the coprocessor before the coprocessor instruction is issued to a processor. The execution of the copied coprocessor instruction is completed based on information received from the processor after the coprocessor instruction has been issued to the processor.