Patents by Inventor Yusuke Dohmae

Yusuke Dohmae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240008277
    Abstract: A semiconductor wafer according to the present embodiment includes a plurality of semiconductor chip regions and a division region. The plurality of semiconductor chip regions have a semiconductor element. The division region is provided between the semiconductor chip regions adjacent to each other. A first stacked body is provided on the division region. The first stacked body is configured with a plurality of first material films and a plurality of second material films alternately stacked.
    Type: Application
    Filed: September 19, 2023
    Publication date: January 4, 2024
    Applicant: KIOXIA CORPORATION
    Inventors: Takanobu ONO, Yusuke DOHMAE
  • Patent number: 11800709
    Abstract: A semiconductor wafer according to the present embodiment includes a plurality of semiconductor chip regions and a division region. The plurality of semiconductor chip regions have a semiconductor element. The division region is provided between the semiconductor chip regions adjacent to each other. A first stacked body is provided on the division region. The first stacked body is configured with a plurality of first material films and a plurality of second material films alternately stacked.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: October 24, 2023
    Assignee: Kioxia Corporation
    Inventors: Takanobu Ono, Yusuke Dohmae
  • Publication number: 20210167085
    Abstract: A semiconductor wafer according to the present embodiment includes a plurality of semiconductor chip regions and a division region. The plurality of semiconductor chip regions have a semiconductor element. The division region is provided between the semiconductor chip regions adjacent to each other. A first stacked body is provided on the division region. The first stacked body is configured with a plurality of first material films and a plurality of second material films alternately stacked.
    Type: Application
    Filed: February 4, 2021
    Publication date: June 3, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takanobu ONO, Yusuke DOHMAE
  • Patent number: 10950621
    Abstract: A semiconductor wafer according to the present embodiment includes a plurality of semiconductor chip regions and a division region. The plurality of semiconductor chip regions have a semiconductor element. The division region is provided between the semiconductor chip regions adjacent to each other. A first stacked body is provided on the division region. The first stacked body is configured with a plurality of first material films and a plurality of second material films alternately stacked.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: March 16, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takanobu Ono, Yusuke Dohmae
  • Patent number: 10892191
    Abstract: A method of manufacturing a semiconductor device, includes irradiating a division region of a semiconductor wafer with laser to form a plurality of modified portions arranged in a direction along the division region in the semiconductor wafer, and splitting the semiconductor wafer into a plurality of semiconductor chips using a groove generated from the plurality of modified portions in the semiconductor wafer. The plurality of modified portions is at a first interval in a first part of the division region and at a second interval smaller than the first interval in a second part of the division region.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: January 12, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takanobu Ono, Yusuke Dohmae
  • Publication number: 20200058676
    Abstract: A semiconductor wafer according to the present embodiment includes a plurality of semiconductor chip regions and a division region. The plurality of semiconductor chip regions have a semiconductor element. The division region is provided between the semiconductor chip regions adjacent to each other. A first stacked body is provided on the division region. The first stacked body is configured with a plurality of first material films and a plurality of second material films alternately stacked.
    Type: Application
    Filed: February 26, 2019
    Publication date: February 20, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takanobu ONO, Yusuke Dohmae
  • Publication number: 20200058550
    Abstract: A method of manufacturing a semiconductor device, includes irradiating a division region of a semiconductor wafer with laser to form a plurality of modified portions arranged in a direction along the division region in the semiconductor wafer, and splitting the semiconductor wafer into a plurality of semiconductor chips using a groove generated from the plurality of modified portions in the semiconductor wafer. The plurality of modified portions is at a first interval in a first part of the division region and at a second interval smaller than the first interval in a second part of the division region.
    Type: Application
    Filed: March 1, 2019
    Publication date: February 20, 2020
    Inventors: Takanobu ONO, Yusuke DOHMAE
  • Patent number: 8896111
    Abstract: In one embodiment, a semiconductor device includes a first semiconductor chip disposed on a circuit board, an adhesive layer fixing the first semiconductor chip to the circuit board, and a second semiconductor chip having an outer shape smaller than that of the first semiconductor chip. At least a part of the second semiconductor chip is embedded in the adhesive layer. The adhesive layer has a thickness in a range of 95 to 150 ?m. The adhesive layer includes a cured product of a thermosetting resin whose thermal time viscosity at a time that the second semiconductor chip is embedded is in a range of 500 to 5000 Pa·s.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: November 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Tanimoto, Takashi Imoto, Yoriyasu Ando, Masashi Noda, Naoki Iwamasa, Koichi Miyashita, Masatoshi Kawato, Masaji Iwamoto, Jun Tanaka, Yusuke Dohmae
  • Patent number: 8404567
    Abstract: A manufacturing method of a semiconductor device, includes: forming grooves from a first surface side of a semiconductor wafer; separating plural chip areas into pieces by grinding a second surface of the semiconductor wafer after a protection sheet is attached to the first surface of the semiconductor wafer; attaching a laminated film in which a dicing film and an adhesive film are sequentially laminated on a supporting film composed of a resin film with high modulus of elasticity to the second surface of the semiconductor wafer; and cutting the adhesive film.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: March 26, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yusuke Dohmae
  • Publication number: 20100227454
    Abstract: A manufacturing method of a semiconductor device, includes: forming grooves from a first surface side of a semiconductor wafer; separating plural chip areas into pieces by grinding a second surface of the semiconductor wafer after a protection sheet is attached to the first surface of the semiconductor wafer; attaching a laminated film in which a dicing film and an adhesive film are sequentially laminated on a supporting film composed of a resin film with high modulus of elasticity to the second surface of the semiconductor wafer; and cutting the adhesive film.
    Type: Application
    Filed: March 2, 2010
    Publication date: September 9, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yusuke DOHMAE