Patents by Inventor Yusuke Dohmae
Yusuke Dohmae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250081463Abstract: A semiconductor wafer according to the present embodiment includes a plurality of semiconductor chip regions and a division region. The plurality of semiconductor chip regions have a semiconductor element. The division region is provided between the semiconductor chip regions adjacent to each other. A first stacked body is provided on the division region. The first stacked body is configured with a plurality of first material films and a plurality of second material films alternately stacked.Type: ApplicationFiled: November 20, 2024Publication date: March 6, 2025Applicant: KIOXIA CORPORATIONInventors: Takanobu ONO, Yusuke DOHMAE
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Patent number: 12185547Abstract: A semiconductor wafer according to the present embodiment includes a plurality of semiconductor chip regions and a division region. The plurality of semiconductor chip regions have a semiconductor element. The division region is provided between the semiconductor chip regions adjacent to each other. A first stacked body is provided on the division region. The first stacked body is configured with a plurality of first material films and a plurality of second material films alternately stacked.Type: GrantFiled: September 19, 2023Date of Patent: December 31, 2024Assignee: KIOXIA CORPORATIONInventors: Takanobu Ono, Yusuke Dohmae
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Publication number: 20240008277Abstract: A semiconductor wafer according to the present embodiment includes a plurality of semiconductor chip regions and a division region. The plurality of semiconductor chip regions have a semiconductor element. The division region is provided between the semiconductor chip regions adjacent to each other. A first stacked body is provided on the division region. The first stacked body is configured with a plurality of first material films and a plurality of second material films alternately stacked.Type: ApplicationFiled: September 19, 2023Publication date: January 4, 2024Applicant: KIOXIA CORPORATIONInventors: Takanobu ONO, Yusuke DOHMAE
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Patent number: 11800709Abstract: A semiconductor wafer according to the present embodiment includes a plurality of semiconductor chip regions and a division region. The plurality of semiconductor chip regions have a semiconductor element. The division region is provided between the semiconductor chip regions adjacent to each other. A first stacked body is provided on the division region. The first stacked body is configured with a plurality of first material films and a plurality of second material films alternately stacked.Type: GrantFiled: February 4, 2021Date of Patent: October 24, 2023Assignee: Kioxia CorporationInventors: Takanobu Ono, Yusuke Dohmae
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Publication number: 20210167085Abstract: A semiconductor wafer according to the present embodiment includes a plurality of semiconductor chip regions and a division region. The plurality of semiconductor chip regions have a semiconductor element. The division region is provided between the semiconductor chip regions adjacent to each other. A first stacked body is provided on the division region. The first stacked body is configured with a plurality of first material films and a plurality of second material films alternately stacked.Type: ApplicationFiled: February 4, 2021Publication date: June 3, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Takanobu ONO, Yusuke DOHMAE
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Patent number: 10950621Abstract: A semiconductor wafer according to the present embodiment includes a plurality of semiconductor chip regions and a division region. The plurality of semiconductor chip regions have a semiconductor element. The division region is provided between the semiconductor chip regions adjacent to each other. A first stacked body is provided on the division region. The first stacked body is configured with a plurality of first material films and a plurality of second material films alternately stacked.Type: GrantFiled: February 26, 2019Date of Patent: March 16, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takanobu Ono, Yusuke Dohmae
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Patent number: 10892191Abstract: A method of manufacturing a semiconductor device, includes irradiating a division region of a semiconductor wafer with laser to form a plurality of modified portions arranged in a direction along the division region in the semiconductor wafer, and splitting the semiconductor wafer into a plurality of semiconductor chips using a groove generated from the plurality of modified portions in the semiconductor wafer. The plurality of modified portions is at a first interval in a first part of the division region and at a second interval smaller than the first interval in a second part of the division region.Type: GrantFiled: March 1, 2019Date of Patent: January 12, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takanobu Ono, Yusuke Dohmae
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Publication number: 20200058550Abstract: A method of manufacturing a semiconductor device, includes irradiating a division region of a semiconductor wafer with laser to form a plurality of modified portions arranged in a direction along the division region in the semiconductor wafer, and splitting the semiconductor wafer into a plurality of semiconductor chips using a groove generated from the plurality of modified portions in the semiconductor wafer. The plurality of modified portions is at a first interval in a first part of the division region and at a second interval smaller than the first interval in a second part of the division region.Type: ApplicationFiled: March 1, 2019Publication date: February 20, 2020Inventors: Takanobu ONO, Yusuke DOHMAE
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Publication number: 20200058676Abstract: A semiconductor wafer according to the present embodiment includes a plurality of semiconductor chip regions and a division region. The plurality of semiconductor chip regions have a semiconductor element. The division region is provided between the semiconductor chip regions adjacent to each other. A first stacked body is provided on the division region. The first stacked body is configured with a plurality of first material films and a plurality of second material films alternately stacked.Type: ApplicationFiled: February 26, 2019Publication date: February 20, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Takanobu ONO, Yusuke Dohmae
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Patent number: 8896111Abstract: In one embodiment, a semiconductor device includes a first semiconductor chip disposed on a circuit board, an adhesive layer fixing the first semiconductor chip to the circuit board, and a second semiconductor chip having an outer shape smaller than that of the first semiconductor chip. At least a part of the second semiconductor chip is embedded in the adhesive layer. The adhesive layer has a thickness in a range of 95 to 150 ?m. The adhesive layer includes a cured product of a thermosetting resin whose thermal time viscosity at a time that the second semiconductor chip is embedded is in a range of 500 to 5000 Pa·s.Type: GrantFiled: March 12, 2013Date of Patent: November 25, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Akira Tanimoto, Takashi Imoto, Yoriyasu Ando, Masashi Noda, Naoki Iwamasa, Koichi Miyashita, Masatoshi Kawato, Masaji Iwamoto, Jun Tanaka, Yusuke Dohmae
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Patent number: 8404567Abstract: A manufacturing method of a semiconductor device, includes: forming grooves from a first surface side of a semiconductor wafer; separating plural chip areas into pieces by grinding a second surface of the semiconductor wafer after a protection sheet is attached to the first surface of the semiconductor wafer; attaching a laminated film in which a dicing film and an adhesive film are sequentially laminated on a supporting film composed of a resin film with high modulus of elasticity to the second surface of the semiconductor wafer; and cutting the adhesive film.Type: GrantFiled: March 2, 2010Date of Patent: March 26, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Yusuke Dohmae
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Publication number: 20100227454Abstract: A manufacturing method of a semiconductor device, includes: forming grooves from a first surface side of a semiconductor wafer; separating plural chip areas into pieces by grinding a second surface of the semiconductor wafer after a protection sheet is attached to the first surface of the semiconductor wafer; attaching a laminated film in which a dicing film and an adhesive film are sequentially laminated on a supporting film composed of a resin film with high modulus of elasticity to the second surface of the semiconductor wafer; and cutting the adhesive film.Type: ApplicationFiled: March 2, 2010Publication date: September 9, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Yusuke DOHMAE