Abstract: An XTC circuit includes delay circuits, differentiated signal generating circuits, and an amplitude adjusting and adding circuit. A signal Da, which is one aggressor signal, is input to the differentiated signal generating circuit after being delayed by the delay circuit, and the differentiated signal generating circuit generates a differentiated signal having a differentiated waveform of the signal Da. In the amplitude adjusting and adding circuit, the differentiated signal generated by the differentiated signal generating circuit is amplitude-adjusted to become a current signal, and the differentiated signal after the amplitude adjustment is current-added to the signal Db.

Abstract: A multi-lane serializer device 1 includes serializer circuits 101 to 10N and a controller 20. A phase difference detector of each serializer circuit detects a phase difference between a load signal and a first clock, and outputs an abnormal detection signal to the controller 20 when the detected phase difference is abnormal. When the controller 20 receives the abnormal detection signal from any of the serializer circuits, the controller 20 transmits a batch reset instruction signal to all the serializer circuits. Then, in all the serializer circuits, when a reset signal generator receives the batch reset instruction signal output from the controller 20, the reset signal generator transmits a reset instruction signal to a load signal generator to reset the operation of a load signal generation in the load signal generator.

Abstract: A transmitting and receiving device includes a controller, a driver, a specific pattern generator, a transmitting signal detector, an amplifier, a differential amplifier, an average current detector, and a received signal detector. In a non-signal period, the controller causes a current signal to be input from the driver to a laser diode and causes an optical signal to be output from the laser diode. When an optical signal of a specific pattern output from the other-side laser diode reaches a photodiode over a period of length that depends on an average value of a current signal output from the other-side photodiode that receives the optical signal, the controller adjusts a magnitude of the current signal input from the driver to the laser diode based on the length of the period of the optical signal of the specific pattern.

Abstract: A transmitting and receiving device includes a controller, a driver, a specific pattern generator, a transmitting signal detector, an amplifier, a differential amplifier, an average current detector, and a received signal detector. In a non-signal period, the controller causes a current signal to be input from the driver to a laser diode and causes an optical signal to be output from the laser diode. When an optical signal of a specific pattern output from the other-side laser diode reaches a photodiode over a period of length that depends on an average value of a current signal output from the other-side photodiode that receives the optical signal, the controller adjusts a magnitude of the current signal input from the driver to the laser diode based on the length of the period of the optical signal of the specific pattern.

Abstract: A PLL circuit includes a phase comparator, a charge pump, a loop filter, a voltage-controlled oscillator, a frequency divider, a frequency difference determination unit, and an FV characteristics adjustment unit. The frequency difference determination unit determines whether or not a frequency difference between a feedback oscillation signal and an input signal is equal to or smaller than a threshold value. The FV characteristics adjustment unit selects a frequency band in the voltage-controlled oscillator and adjusts FV characteristics.

Abstract: A multi-lane serializer device 1 includes serializer circuits 101 to 10N and a controller 20. A phase difference detector of each serializer circuit detects a phase difference between a load signal and a first clock, and outputs an abnormal detection signal to the controller 20 when the detected phase difference is abnormal. When the controller 20 receives the abnormal detection signal from any of the serializer circuits, the controller 20 transmits a batch reset instruction signal to all the serializer circuits. Then, in all the serializer circuits, when a reset signal generator receives the batch reset instruction signal output from the controller 20, the reset signal generator transmits a reset instruction signal to a load signal generator to reset the operation of a load signal generation in the load signal generator.

Abstract: It is intended to conveniently determine the pharmacokinetics of axitinib and to predict the therapeutic effect of axitinib. The present invention provides a method for determining the pharmacokinetics of axitinib, comprising the step of calculating a predicted pharmacokinetic parameter of axitinib using specific gene polymorphisms and background factors regarding a test subject.

Abstract: Provided is an inkjet adhesive which is applied using an inkjet device, wherein the adhesive can suppress generation of voids in the adhesive layer and, after bonding, can enhance adhesiveness, moisture-resistant adhesion reliability, and cooling/heating cycle reliability. An inkjet adhesive according to the present invention comprises a photocurable compound, a photo-radical initiator, a thermosetting compound having one or more cyclic ether groups or cyclic thioether groups, and a compound capable of reacting with the thermosetting compound, and the compound capable of reacting with the thermosetting compound contains aromatic amine.

Abstract: An XTC circuit includes delay circuits, differentiated signal generating circuits, and an amplitude adjusting and adding circuit. A signal Da, which is one aggressor signal, is input to the differentiated signal generating circuit after being delayed by the delay circuit, and the differentiated signal generating circuit generates a differentiated signal having a differentiated waveform of the signal Da. In the amplitude adjusting and adding circuit, the differentiated signal generated by the differentiated signal generating circuit is amplitude-adjusted to become a current signal, and the differentiated signal after the amplitude adjustment is current-added to the signal Db.

Abstract: A transmission/reception system 1 includes a transmission device 10 and a reception device 20 that is connected to each other through differential signal lines 30 and a signal line 40, and receives a differential signal that is sent out from the transmission device 10 using the reception device 20. The transmission device 10 includes a signal output unit 11, a request input unit 12, and a resistor 13. The signal output unit 11 sends out a differential signal from a pair of output terminals P111 and P112 that are connected to the differential signal lines 30. A common voltage of each of the pair of output terminals P111 and P112 is constant over a state where no electric power is supplied and an idle state.

Abstract: A signal-multiplexing device according to the present embodiment has a structure that is capable of satisfactorily handling an increase in a data rate. The signal-multiplexing device includes M pre-stage buffers and an output buffer. An m-th pre-stage buffer Bm outputs an m-th input signal when the signal levels of both an m-th control signal Cm and an n-th control signal Cn of M control signals are significant, and the m-th pre-stage buffer Bm enters into a high-impedance state when the signal level of at least one of the m-th control signal Cm and the n-th control signal Cn is non-significant. The output buffer Bout sequentially outputs input signals that have been respectively outputted from the M pre-stage buffers at different timings.

Abstract: A signal-multiplexing device according to the present embodiment has a structure that is capable of satisfactorily handling an increase in a data rate. The signal-multiplexing device includes M pre-stage buffers and an output buffer. An m-th pre-stage buffer Bm outputs an m-th input signal when the signal levels of both an m-th control signal Cm and an n-th control signal Cn of M control signals are significant, and the m-th pre-stage buffer Bm enters into a high-impedance state when the signal level of at least one of the m-th control signal Cm and the n-th control signal Cn is non-significant. The output buffer Bout sequentially outputs input signals that have been respectively outputted from the M pre-stage buffers at different timings.

Abstract: An electrode catalyst layer of an electrochemical device is an electrode catalyst layer of an electrochemical device, the electrode catalyst layer including a mesoporous carbon; a catalyst metal supported at least in the mesoporous carbon; and an ionomer. Before supporting the catalyst metal, the mesoporous carbon has mesopores with a mode radius of 1 nm to 25 nm and a pore volume of 1.0 cm3/g to 3.0 cm3/g and has an average particle diameter of 200 nm or more.

Abstract: This embodiment relates to a transmitter that has a structure to suppress an increase in device occupancy area on a semiconductor substrate. The transmitter includes an output driver, a duplication driver, a reference voltage generation unit, a first selection unit, a second selection unit, a comparison unit, and a control unit. The first selection unit selects a first or second test voltage outputted from a duplication driver in which a resistance value is set in cooperation with the output driver. The second selection unit selects a first or second reference voltage outputted from the reference voltage generation unit. The comparison unit compares magnitudes of the first test voltage and the first reference voltage during a first operation period and compares magnitudes of the second test voltage and the second reference voltage during a second operation period different from the first operation period.

Abstract: A PLL circuit of one embodiment has a structure for preferably setting the FV characteristic of an LC-VCO. The PLL circuit includes a voltage controlled oscillator, a phase comparator, a charge pump, a loop filter, and an FV characteristic adjustment unit setting the FV characteristic. The voltage controlled oscillator has an FV characteristic indicating the relationship between a control signal and a frequency and outputs an oscillation signal having a frequency corresponding to the control signal based on the FV characteristic. The phase comparator detects a phase difference between an input signal and the control signal. The charge pump outputs a corrected voltage value changed according to the phase difference. The loop filter outputs a control voltage value changed in response to corrected voltage value variations. The FV characteristic adjustment unit generates an FV characteristic control signal by a mean corrected voltage value.

Abstract: The parameter determination method according to the present disclosure is a parameter determination method for determining a value of a parameter that is used for a simulation of determining gas transportability in a space inside a pore and that defines a boundary condition at an interface between a wall surface and gas or ions inside the pore, the method including determining the value of a parameter that reproduces a first concentration ratio indicating a ratio of the gas or ion concentration inside the pore to the gas or ion concentration outside the pore as the value of the parameter that defines the boundary condition.

Abstract: An apparatus includes a proton-conducting electrolyte membrane, an anode, a cathode, a first flow path which is disposed on the anode and through which an anode fluid containing hydrogen as a constituent element flows, a second flow path which is disposed on the cathode and through which hydrogen flows, a voltage applicator, a detector which detects a hydrogen cross leak amount passing through the membrane, where the detector detects the hydrogen cross leak amount from, a natural potential of one electrode of the cathode and the anode after forming a state where hydrogen is present at the one electrode and hydrogen is not present at the other electrode of the cathode and the anode, or a current flowing between the anode and the cathode when the voltage is applied from the voltage applicator in a state where the first flow path and the second flow path are both sealed off.

Abstract: A PLL circuit includes a phase comparator, a charge pump, a loop filter, a voltage-controlled oscillator, a frequency divider, a frequency difference determination unit, and an FV characteristics adjustment unit. The frequency difference determination unit determines whether or not a frequency difference between a feedback oscillation signal and an input signal is equal to or smaller than a threshold value. The FV characteristics adjustment unit selects a frequency band in the voltage-controlled oscillator and adjusts FV characteristics.

Abstract: The signal multiplexer 1 inputs two selection signals CLK<1>, CLK<2> that sequentially reach significant levels, inputs two input signals IN<1>, IN<2>, and outputs, from an output terminal 14, a signal OUT that depends on an m-th input signal IN<m> of the two input signals when an m-th selection signal CLK<m> of the two selection signals is at the significant level. The signal multiplexer 1 includes a resistance unit 20 and two drive units 301, 302. Each of the drive units 30m includes a driving switch 31m, a selecting switch 32m, and a potential stabilizing switch 33m. When one of the selecting switch 32m and the potential stabilizing switch 33m in each of the drive units 30m is in a closed state, the other is in an open state.

Abstract: A duty compensation device of one embodiment has a structure capable of more accurately setting a duty of a clock within an appropriate range. The duty compensation device comprises a duty adjusting unit, a duty measuring unit, a controlling unit. The duty measuring unit generates a sampling clock of a frequency fn that is asynchronous to the clock over an n-th period Tn (n=1 to N and N is an integer of 3 or more), and obtains measurement information for specifying the duty of the clock by using the sampling clock. The controlling unit determines a control code to be given to the duty adjusting unit based on control code candidates obtained for each of the N periods T1 to TN and the control code candidates in which the duty specified by measurement information obtained by the duty measuring unit is within a predetermined range.