Abstract: To suppress an increase in RC-IGBT recovery loss. In a semiconductor device, an IGBT region includes a base layer of a second conductivity type in a surface layer of a drift layer, a diode region includes an anode layer of a second conductivity type in the surface layer of the drift layer, a termination region includes a well layer of the second conductivity type in the surface layer of the drift layer, an impurity concentration profile of the base layer and an impurity concentration profile of the anode layer in a direction along an upper surface of the drift layer cyclically fluctuate, and the impurity concentration profile of the base layer and the impurity concentration profile of the anode layer are different.

Abstract: An expansion tank, includes: a tank main body defining a storage chamber storing a coolant liquid therein; multiple partition walls provided in the tank main body to divide the storage chamber into multiple division chambers including an inlet chamber and an outlet chamber, the partition walls being formed with communication holes for bringing adjacent ones of the division chambers into communication with each other; a coolant liquid inlet portion that is provided on the tank main body and is open to the inlet chamber; a coolant liquid outlet portion that has an outlet opening in a depression formed in a bottom of the tank main body and is open to the outlet chamber; and a barrier wall extending from a side wall of the tank main body or one of the partition walls into the depression.

Abstract: An expansion tank, includes: a tank main body defining a storage chamber storing a coolant liquid therein; multiple partition walls provided in the tank main body to divide the storage chamber into multiple division chambers including an inlet chamber and an outlet chamber, the partition walls being formed with communication holes for bringing adjacent ones of the division chambers into communication with each other; a coolant liquid inlet portion that is provided on the tank main body and is open to the inlet chamber; a coolant liquid outlet portion that has an outlet opening in a depression formed in a bottom of the tank main body and is open to the outlet chamber; and a barrier wall extending from a side wall of the tank main body or one of the partition walls into the depression.

Abstract: An internal combustion engine, includes: a cylinder block; a crankshaft rotatably supported in the cylinder block; an oil pan fastened to a lower end portion of the cylinder block; a chain case fastened to one end wall of the cylinder block in an axial direction of the crankshaft; a belt wound around a crank pulley provided on an end portion of the crankshaft protruding from the chain case and an accessory pulley provided on an engine accessory; and a tensioner contacting a back surface of the belt and applying a tension to the belt, wherein the tensioner includes multiple fastening portions, such that one of the fastening portions is fastened to at least one of the cylinder block and the chain case, and another one of the fastening portions is fastened to the oil pan.

Abstract: An internal combustion engine, includes: a cylinder block; a crankshaft rotatably supported in the cylinder block; an oil pan fastened to a lower end portion of the cylinder block; a chain case fastened to one end wall of the cylinder block in an axial direction of the crankshaft; a belt wound around a crank pulley provided on an end portion of the crankshaft protruding from the chain case and an accessory pulley provided on an engine accessory; and a tensioner contacting a back surface of the belt and applying a tension to the belt, wherein the tensioner includes multiple fastening portions, such that one of the fastening portions is fastened to at least one of the cylinder block and the chain case, and another one of the fastening portions is fastened to the oil pan.

Abstract: A semiconductor device includes a first semiconductor layer on one main surface of a semiconductor substrate; a plurality of trench gates in the first semiconductor layer extending to reach the inside of the semiconductor substrate; a second semiconductor layer selectively provided in an upper portion of the first semiconductor layer between the trench gates; an isolation layer in contact with a side surface of the second semiconductor layer and extends in the first semiconductor; and a third semiconductor layer in the upper portion of the first semiconductor layer between the trench gates and has at least one side surface in contact with the trench gate. The isolation layer is between and separates the second semiconductor layer and the third semiconductor layer from each other and is formed to extend to the same depth as, or to a position deeper than the second semiconductor layer.

Abstract: A p-type base layer (2) is formed on a surface of an n-type silicon substrate (1). First and second n+-type buffer layers (8,9) 9 are formed on a back surface of the n-type silicon substrate (1). The first n+-type buffer layer (8) is formed by a plurality of implantations of protons at different accelerating voltages and has a plurality of peak concentrations with different depths from the back surface of the n-type silicon substrate (1). The second n+-type buffer layer (9) is formed by an implantation of a phosphorus. A position of a peak concentration of the phosphorus is shallower from the back surface of the n-type silicon substrate (1) than positions of peak concentrations of the protons. The peak concentration of the phosphorus is higher than the peak concentrations of the protons. A concentration of the protons is higher than a concentration of the phosphorus at the positions of the peak concentrations of the protons.

Abstract: Included are a semiconductor substrate, an emitter electrode formed on the semiconductor substrate, a gate electrode formed on the semiconductor substrate, a source layer of a first conductivity type formed on the semiconductor substrate, a base layer of a second conductivity type formed on the semiconductor substrate, a collector electrode formed under the semiconductor substrate, a plurality of active trench gates formed on a top-surface side of the semiconductor substrate and connected to the gate electrode, and a plurality of dummy trench gates formed on the top-surface side of the semiconductor substrate and not connected to the gate electrode. First structures, each including three or more of the active trench gates arranged side by side, and second structures, each including three or more of the dummy trench gates arranged side by side, are alternately provided.

Abstract: A p-type base layer (2) is formed on a surface of an n-type silicon substrate (1). First and second n+-type buffer layers (8,9) 9 are formed on a back surface of the n-type silicon substrate (1). The first n+-type buffer layer (8) is formed by a plurality of implantations of protons at different accelerating voltages and has a plurality of peak concentrations with different depths from the back surface of the n-type silicon substrate (1). The second n+-type buffer layer (9) is formed by an implantation of a phosphorus. A position of a peak concentration of the phosphorus is shallower from the back surface of the n-type silicon substrate (1) than positions of peak concentrations of the protons. The peak concentration of the phosphorus is higher than the peak concentrations of the protons. A concentration of the protons is higher than a concentration of the phosphorus at the positions of the peak concentrations of the protons.

Abstract: A method for manufacturing a silicon carbide semiconductor device comprises: a step for forming a front-surface electrode (30) on a front surface side of a silicon carbide wafer (10); a step for thinning the silicon carbide wafer (10) by reducing a thickness of the silicon carbide wafer (10) from a back surface side thereof; a step for providing a metal layer (21) on the back surface of the thinned silicon carbide wafer (10); a step for irradiating the metal layer (21) with laser light, while applying an external force such that the silicon carbide wafer and the metal layer are planarized, to form the carbide layer (20) obtained by a reaction with carbon in the silicon carbide wafer (10), on a back surface side of the metal layer (21); and a step for forming a back-surface electrode (40) on a back surface side of the carbide layer (20).

Abstract: Formed in a pinion (74) are pinion-side helical external teeth (74A) that mesh with a ring gear 823), and pinion-side helical internal teeth (74a) that mesh with a pinion inner (71). Formed in the pinion inner (71) are pinion inner-side helical external teeth (73) that mesh with the pinion-side helical internal teeth (74a). The configuration is formed so that when the rotational speed of the pinion (74) is slower than that of the ring gear (23), a thrust load is generated in a direction toward the ring gear (23), and when the rotational speed of the pinion (74) is faster than that of the ring gear (23), a thrust load is generated in a direction away from the ring gear (23).

Abstract: A starter includes an output shaft which rotates by a rotary force applied from the motor unit, a housing in which an end of the output shaft is rotatably supported, and an electromagnetic device configured to apply/shut off current to the motor unit, and biases a suppressing force toward the ring gear to the pinion gear through a clutch mechanism, wherein a load receiving member which abuts one end of the output shaft to receive an axial load generated from the output shaft is installed in the housing.

Abstract: A semiconductor device includes a first semiconductor layer on one main surface of a semiconductor substrate; a plurality of trench gates in the first semiconductor layer extending to reach the inside of the semiconductor substrate; a second semiconductor layer selectively provided in an upper portion of the first semiconductor layer between the trench gates; an isolation layer in contact with a side surface of the second semiconductor layer and extends in the first semiconductor; and a third semiconductor layer in the upper portion of the first semiconductor layer between the trench gates and has at least one side surface in contact with the trench gate. The isolation layer is between and separates the second semiconductor layer and the third semiconductor layer from each other and is formed to extend to the same depth as, or to a position deeper than the second semiconductor layer.

Abstract: Formed in a pinion (74) are pinion-side helical external teeth (74A) that mesh with a ring gear 823), and pinion-side helical internal teeth (74a) that mesh with a pinion inner (71). Formed in the pinion inner (71) are pinion inner-side helical external teeth (73) that mesh with the pinion-side helical internal teeth (74a). The configuration is formed so that when the rotational speed of the pinion (74) is slower than that of the ring gear (23), a thrust load is generated in a direction toward the ring gear (23), and when the rotational speed of the pinion (74) is faster than that of the ring gear (23), a thrust load is generated in a direction away from the ring gear (23).

Abstract: An object of the present invention is to provide at a low cost a light emitting device capable of emitting light not only in a visible light region, but also in an ultraviolet ray region and an infrared ray region with a high luminance and, further, capable of being reduced in size. According to the present invention, in the light emitting device (1) in which a light emitting electrode (4) and a cold cathode (3) are disposed opposite to each other, the light emitting electrode (4) is constituted by a metal oxide structure having whiskers (15) of a metal oxide. As for the metal oxide which constitutes the whiskers, it is preferable to use such metal oxide as has a band gap of from 1.5 to 7.7 eV. The light emitting electrode and the cold cathode are disposed within a vacuum chamber or a container having a base body sealed therein.