Patents by Inventor Yusuke Fukuda

Yusuke Fukuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7544552
    Abstract: A method for manufacturing a junction semiconductor device, having a step for forming a first high-resistance layer, a step for forming a channel-doped layer, a step for forming a second high-resistance layer, a step for forming a low-resistance layer of a first conductive type that acts as a source region, a step for performing partial etching to a midway depth of the second high-resistance layer and the low-resistance layer, a step for forming a gate region below the portion etched in the etching step, and a step for forming a protective film on the surface of the region between the gate region and the source region. A gate region is formed using relatively low energy ion implantation in the surface that has been etched in advance to a height that is between the lower surface of the source area and the upper surface of the channel-doped layer.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: June 9, 2009
    Assignees: Honda Motor Co., Ltd., Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Ken-ichi Nonaka, Hideki Hashimoto, Seiichi Yokoyama, Kensuke Iwanaga, Yoshimitsu Saito, Hiroaki Iwakuro, Masaaki Shimizu, Yusuke Fukuda, Koichi Nishikawa, Yusuke Maeyama
  • Publication number: 20090000120
    Abstract: By finding a range of an allowable error of maximum meshing position of a worm shaft in an axial direction relative to a worm wheel, that is higher than that of a worm shaft of a conventional worm gear unit, a worm gear unit of the present invention is provided.
    Type: Application
    Filed: June 26, 2007
    Publication date: January 1, 2009
    Inventors: Kohtaro Shiino, Yusuke Fukuda
  • Publication number: 20070192473
    Abstract: A performance information monitoring method using computers includes the steps of accepting information on a group relating to a first computer in the first computer; storing the accepted group information in a storage in the first computer; accepting performance information from a second computer in the first computer; comparing performance information of the second computer previously stored in a storage with the performance information received from the second computer in the first computer; judging whether or not the second computer is included in the information of the group when finding a difference between the performance information in the comparison result; and transmitting an instruction to the computer included in the group information to change a performance information collection interval according to the judgment result.
    Type: Application
    Filed: March 21, 2007
    Publication date: August 16, 2007
    Inventors: Yusuke Fukuda, Tadashi Numanoi, Tomohiro Kominami, Naoki Shimada
  • Publication number: 20070130564
    Abstract: The present invention relates to a computer system, more particularly to a computer system for reducing a performance load generated by the operation of a program for obtaining performance information of a storage system. A performance information collecting method executed in a computer system comprising: the performance information collecting method comprises: a first step of obtaining, by the control unit, the performance information of the storage system; a second step of transmitting, by the control unit, the obtained performance information to the host computer having a lower load than a predetermined threshold value; a third step of transmitting, by the host computer, the performance information transmitted from the control unit to the management computer; and a fourth step of collecting, by the management computer the transmitted performance information.
    Type: Application
    Filed: December 13, 2005
    Publication date: June 7, 2007
    Inventor: Yusuke Fukuda
  • Patent number: 7209863
    Abstract: A performance information monitoring method using computers includes the steps of accepting information on a group relating to a first computer in the first computer; storing the accepted group information in a storage in the first computer; accepting performance information from a second computer in the first computer; comparing performance information of the second computer previously stored in a storage with the performance information received from the second computer in the first computer; judging whether or not the second computer is included in the information of the group when finding a difference between the performance information in the comparison result; and transmitting an instruction to the computer included in the group information to change a performance information collection interval according to the judgment result.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: April 24, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Yusuke Fukuda, Tadashi Numanoi, Tomohiro Kominami, Naoki Shimada
  • Publication number: 20070032002
    Abstract: A method for manufacturing an ion implantation mask is disclosed which includes the steps of: forming an oxide film as a protective film over the entire surface of a semiconductor substrate; forming a thin metal film over the oxide film; and forming an ion-inhibiting layer composed of an ion-inhibiting metal over the thin metal film. The obtained ion implantation mask is used to form a deeper selectively electroconductive region.
    Type: Application
    Filed: August 1, 2006
    Publication date: February 8, 2007
    Applicants: HONDA MOTOR CO., LTD., Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Ken-ichi Nonaka, Hideki Hashimoto, Seiichi Yokoyama, Hiroaki Iwakuro, Koichi Nishikawa, Masaaki Shimizu, Yusuke Fukuda
  • Publication number: 20060214268
    Abstract: A semiconductor device includes: a passivation film; a first semiconductor layer that has a first main component of 4H—SiC of a first conductivity type; and a second semiconductor layer that has a second main component of 4H—SiC of a second conductivity type. The second semiconductor layer has a pn-junction with the first semiconductor layer. The pn-junction has a junction edge. The first and second semiconductor layers further include a local area that includes the junction edge. The local area has a first principal plane that interfaces with the passivation film. A normal to the first principal plane tilts by a first tilt angle in a range of 25 degrees to 45 degrees from a first axis of [0001] or [000-1] toward a second axis of <01-10>.
    Type: Application
    Filed: March 22, 2006
    Publication date: September 28, 2006
    Inventors: Yusuke Maeyama, Koichi Nishikawa, Yusuke Fukuda, Masaaki Shimizu, Masashi Satoh, Hiroaki Iwakuro, Kenichi Nonaka
  • Publication number: 20060216879
    Abstract: A method for manufacturing a junction semiconductor device, having a step for forming a first high-resistance layer, a step for forming a channel-doped layer, a step for forming a second high-resistance layer, a step for forming a low-resistance layer of a first conductive type that acts as a source region, a step for performing partial etching to a midway depth of the second high-resistance layer and the low-resistance layer, a step for forming a gate region below the portion etched in the etching step, and a step for forming a protective film on the surface of the region between the gate region and the source region. A gate region is formed using relatively low energy ion implantation in the surface that has been etched in advance to a height that is between the lower surface of the source area and the upper surface of the channel-doped layer.
    Type: Application
    Filed: March 23, 2006
    Publication date: September 28, 2006
    Inventors: Ken-ichi Nonaka, Hideki Hashimoto, Seiichi Yokoyama, Kensuke Iwanaga, Yoshimitsu Saito, Hiroaki Iwakuro, Masaaki Shimizu, Yusuke Fukuda, Koichi Nishikawa, Yusuke Maeyama
  • Publication number: 20040210418
    Abstract: A performance information monitoring method using computers includes the steps of accepting information on a group relating to a first computer in the first computer; storing the accepted group information in a storage in the first computer; accepting performance information from a second computer in the first computer; comparing performance information of the second computer previously stored in a storage with the performance information received from the second computer in the first computer; judging whether or not the second computer is included in the information of the group when finding a difference between the performance information in the comparison result; and transmitting an instruction to the computer included in the group information to change a performance information collection interval according to the judgment result.
    Type: Application
    Filed: August 6, 2003
    Publication date: October 21, 2004
    Inventors: Yusuke Fukuda, Tadashi Numanoi, Tomohiro Kominami, Naoki Shimada