Abstract: A semiconductor device includes a second deep layer between a first deep layer and first current distribution layer and a base region in an active region and in a part of an inactive region adjacent to the active region. The second deep layer has a second stripe portion including lines connecting to the base region and the first deep layer. The semiconductor device further includes a second current distribution layer between the first current distribution layer and the base region and arranged between the lines of the second stripe portion. The first deep layer has a first stripe portion including a plurality of lines, and each line has an end portion connecting to a frame-shaped portion and an inner portion on an inner side of the end portion. The width of the end portion is equal to or greater than the inner portion.

Abstract: A semiconductor device includes a first main electrode, a second main electrode, and a semiconductor layer. The semiconductor layer includes a p-type semiconductor region disposed at a position exposed from the upper surface of the semiconductor layer and electrically connected to the second main electrode, and an n-type semiconductor region in contact with the p-type semiconductor region and separated from the second main electrode by the p-type semiconductor region. The n-type semiconductor region has a trap region provided at a position in contact with the p-type semiconductor region, and a hole trap is formed in the trap region.

Abstract: A SiC semiconductor device includes a substrate of a first conductivity type, a buffer layer of the first conductivity type on the substrate, a low-concentration layer on the buffer layer, a first deep layer and a JFET portion on the low-concentration layer, a current diffusion layer of the first conductivity type disposed on the JFET portion and having an impurity concentration higher than the low-concentration layer, a second deep layer of a second conductivity type disposed on the first deep layer, a base layer of the second conductivity type disposed on the current diffusion layer and the second deep layer, an impurity region of the first conductivity type disposed in a surface layer portion of the base layer, and a trench gate structure penetrating the impurity region and the base layer and reach the current diffusion layer. The JFET portion is formed with defect portions.