Patents by Inventor Yusuke Horie

Yusuke Horie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240097106
    Abstract: A battery electrode manufacturing device, which can suppress air from being contained in the active material and improve uniformity of an active material layer formed on a current collector, is provided. The battery electrode manufacturing device comprises: a first chamber whose interior is decompressed below atmospheric pressure; an active material supply unit that supplies a powdery active material onto a current collector, which is arranged in the first chamber; and a compressor that compresses the active material supplied on the current collector, wherein the active material supply unit and the compressor are arranged in the first chamber.
    Type: Application
    Filed: November 30, 2021
    Publication date: March 21, 2024
    Inventors: Hideaki HORIE, Kenichiro ENOKI, Yusuke NAKASHIMA
  • Patent number: 7737043
    Abstract: There are provided an inspection method of a compound semiconductor substrate that can have the amount of impurities at the surface of the compound semiconductor substrate reduced, a compound semiconductor substrate, a surface treatment method of a compound semiconductor substrate, and a method of producing a compound semiconductor crystal. In the inspection method of the surface of the compound semiconductor substrate, the surface roughness Rms of the compound semiconductor substrate is measured using an atomic force microscope at the pitch of not more than 0.4 nm in a scope of not more than 0.2 ?m square. The surface roughness Rms of the compound semiconductor substrate measured by the inspection method is not more than 0.2 nm.
    Type: Grant
    Filed: May 16, 2007
    Date of Patent: June 15, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takayuki Nishiura, So Tanaka, Yusuke Horie, Kyoko Okita, Takatoshi Okamoto
  • Patent number: 7619301
    Abstract: A GaAs semiconductor substrate includes a surface layer. When an atomic ratio is to be calculated using a 3d electron spectrum of Ga atoms and As atoms measured at the condition of 10° for the photoelectron take-off angle ? by X-ray photoelectron spectroscopy, the structural atomic ratio of all Ga atoms to all As atoms (Ga)/(As) at the surface layer is at least 0.5 and not more than 0.9, the ratio of As atoms bound with O atoms to all Ga atoms and all As atoms (As—O)/{(Ga)+(As)} at the surface layer is at least 0.15 and not more than 0.35, and the ratio of Ga atoms bound with O atoms to all Ga atoms and all As atoms (Ga—O)/{(Ga)+(As)} at the surface layer is at least 0.15 and not more than 0.35. Accordingly, there is provided a GaAs semiconductor substrate having a surface cleaned to an extent allowing removal of impurities and oxides at the surface by at least thermal cleaning of the substrate.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: November 17, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takayuki Nishiura, Yoshio Mezaki, Yusuke Horie, Yasuaki Higuchi
  • Publication number: 20080296738
    Abstract: A GaAs semiconductor substrate includes a surface layer. When an atomic ratio is to be calculated using a 3d electron spectrum of Ga atoms and As atoms measured at the condition of 10° for the photoelectron take-off angle ? by X-ray photoelectron spectroscopy, the structural atomic ratio of all Ga atoms to all As atoms (Ga)/(As) at the surface layer is at least 0.5 and not more than 0.9, the ratio of As atoms bound with O atoms to all Ga atoms and all As atoms (As—O)/{(Ga)+(As)} at the surface layer is at least 0.15 and not more than 0.35, and the ratio of Ga atoms bound with O atoms to all Ga atoms and all As atoms (Ga—O)/{(Ga)+(As)} at the surface layer is at least 0.15 and not more than 0.35. Accordingly, there is provided a GaAs semiconductor substrate having a surface cleaned to an extent allowing removal of impurities and oxides at the surface by at least thermal cleaning of the substrate.
    Type: Application
    Filed: October 9, 2007
    Publication date: December 4, 2008
    Inventors: Takayuki Nishiura, Yoshio Mezaki, Yusuke Horie, Yasuaki Higuchi
  • Publication number: 20080292877
    Abstract: The present invention provides a method of cleaning a GaAs substrate with less precipitate particles after cleaning. This cleaning method comprises an acid cleaning step (S11), a deionized water rinsing step (S12), and a rotary drying step (S13). First, a GaAs substrate with a mirror finished surface is immersed in an acid cleaning solution in the acid cleaning step (S11). In the acid cleaning step, the cleaning time is less than 30 seconds. Next, the deionized water rinsing step performs the cleaned GaAs substrate with deionized water (S12) to wash away the cleaning solution deposited thereon. Subsequently, the rotary drying step dries the GaAs substrate deposited on deionized water (S13). This provides the cleaned GaAs substrate with less precipitate particles.
    Type: Application
    Filed: April 25, 2005
    Publication date: November 27, 2008
    Inventors: Yusuke Horie, Takayuki Nishiura, Tomoki Uemura
  • Publication number: 20070269989
    Abstract: There are provided an inspection method of a compound semiconductor substrate that can have the amount of impurities at the surface of the compound semiconductor substrate reduced, a compound semiconductor substrate, a surface treatment method of a compound semiconductor substrate, and a method of producing a compound semiconductor crystal. In the inspection method of the surface of the compound semiconductor substrate, the surface roughness Rms of the compound semiconductor substrate is measured using an atomic force microscope at the pitch of not more than 0.4 nm in a scope of not more than 0.2 ?m square. The surface roughness Rms of the compound semiconductor substrate measured by the inspection method is not more than 0.2 nm.
    Type: Application
    Filed: May 16, 2007
    Publication date: November 22, 2007
    Inventors: Takayuki Nishiura, So Tanaka, Yusuke Horie, Kyoko Okita, Takatoshi Okamoto
  • Publication number: 20070207630
    Abstract: A surface treatment method of a compound semiconductor substrate, a fabrication method of a compound semiconductor, a compound semiconductor substrate, and a semiconductor wafer are provided, directed to reducing the impurity concentration at a layer formed on a substrate by reducing the impurity concentration at the surface of the substrate formed of a compound semiconductor. The compound semiconductor substrate surface treatment method includes a substrate preparation step and a first washing step. The substrate preparation step includes the step of preparing a substrate formed of a compound semiconductor containing at least 5 mass % of indium. In the first washing step, the substrate is washed for a washing duration of at least 3 seconds and not more than 60 seconds using washing liquid having a pH of at least ?1 and not more than 3, and an oxidation-reduction potential E (mV) satisfying the relationship of ?0.08333x+0.750?E??0.833x+1.333, where x is the pH value.
    Type: Application
    Filed: March 1, 2007
    Publication date: September 6, 2007
    Inventors: Takayuki Nishiura, Kyoko Okita, Yusuke Horie
  • Publication number: 20060281328
    Abstract: A compound semiconductor substrate includes a substrate composed of a p-type compound semiconductor; and a substance containing p-type impurity atoms, the substance being bonded to a surface of the substrate.
    Type: Application
    Filed: June 6, 2006
    Publication date: December 14, 2006
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takayuki Nishiura, Yusuke Horie, Mitsutaka Tsubokura, Osamu Ohama