Patents by Inventor Yusuke ISHIYAMA

Yusuke ISHIYAMA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240332147
    Abstract: A semiconductor apparatus includes an insulating substrate and an electrode. The insulating substrate includes an insulating layer including a first main surface, and a circuit pattern. The circuit pattern is disposed on the first main surface and includes a first portion. The electrode includes a second portion bonded to the first portion. Bonding between the first portion and the second portion is ultrasonic bonding. One of the first portion and the second portion is fitted in the other of the first portion and the second portion.
    Type: Application
    Filed: March 20, 2024
    Publication date: October 3, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventor: Yusuke ISHIYAMA
  • Publication number: 20240310092
    Abstract: A refrigeration cycle apparatus includes a compressor, a first heat exchanger, a second heat exchanger, a third heat exchanger, an expansion device, a gas-liquid separator, a first flow rate control device, and a switch device configured to switch a route in which refrigerant circulates between a first route and a second route. In the first route, the refrigerant flows in order of the compressor, the first heat exchanger, the expansion device, the second heat exchanger, and the gas-liquid separator, and then, the refrigerant in liquid state discharged from the gas-liquid separator flows into the third heat exchanger. In the second route, the refrigerant flows in order of the compressor, the second heat exchanger, and the gas-liquid separator, and then, the refrigerant in gaseous state discharged from the gas-liquid separator flows through the first flow rate control device into the third heat exchanger.
    Type: Application
    Filed: March 24, 2021
    Publication date: September 19, 2024
    Inventors: Soichiro KOSHI, Takuya MATSUDA, Hiroki ISHIYAMA, Yusuke TASHIRO
  • Publication number: 20230275035
    Abstract: A semiconductor module includes: a fin base including a first surface and a second surface, the second surface being a surface opposite to the first surface; an insulating sheet arranged on the first surface; a plurality of frame patterns arranged on the first surface with the insulating sheet interposed therebetween; a semiconductor element arranged on at least one of the plurality of frame patterns; and a plurality of fins swaged onto the second surface so as to be spaced apart from each other in a first direction.
    Type: Application
    Filed: September 14, 2021
    Publication date: August 31, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hiroyuki YOSHIHARA, Yusuke ISHIYAMA, Yasuyuki SANDA, Kenichi HAYASHI
  • Patent number: 11557531
    Abstract: A semiconductor device includes: a substrate; a semiconductor element arranged on the substrate; a plate-like member electrically connected to the semiconductor element; a first electrode formed on the semiconductor element and joined to the plate-like member with solder; a second electrode formed on the semiconductor element and spaced from the first electrode, and including a metal capable of forming an alloy with the solder; and a metal film formed on the semiconductor element and spaced from the second electrode in a region on the first electrode side as seen from the second electrode, in a two-dimensional view of the semiconductor element as seen from the plate-like member, and including a metal capable of forming an alloy with the solder.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: January 17, 2023
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shohei Ogawa, Junji Fujino, Yusuke Ishiyama, Isao Oshima, Takumi Shigemoto
  • Patent number: 11424178
    Abstract: A semiconductor module includes: an insulated circuit board; a semiconductor device mounted on the insulated circuit board; a printed wiring board arranged above the insulated circuit board and the semiconductor device and having a through-hole; a metal pile having a lower end bonded to an upper surface of the semiconductor device and a cylindrical portion penetrating through the through-hole and bonded to the printed wiring board; a case surrounding the insulated circuit board, the semiconductor device, the printed wiring board and the metal pile; and a sealing material sealing an inside of the case.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: August 23, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Satoshi Kondo, Hidetoshi Ishibashi, Hiroshi Yoshida, Nobuhiro Asaji, Junji Fujino, Yusuke Ishiyama, Hodaka Rokubuichi
  • Patent number: 11398447
    Abstract: A semiconductor device includes an insulating substrate formed by integrating a ceramic base plate and a cooling fin; a multiple of plate interconnection members; and a plurality of semiconductor elements. The one faces of the semiconductor elements are bonded to the ceramic base plate of the insulating substrate with a chip-bottom solder, and the other faces thereof are bonded to the plate-interconnection members with a chip-top solder so that plate interconnection members correspond respectively to the semiconductor elements. The chip-bottom solder and the chip-top solder both contain mainly Sn and 0.3-3 wt. % Ag and 0.5-1 wt. % Cu. This allows the semiconductor device to be reduced in size without impairing heat dissipation.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: July 26, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shohei Ogawa, Junji Fujino, Satoru Ishikawa, Takumi Shigemoto, Yusuke Ishiyama
  • Patent number: 11322452
    Abstract: A semiconductor module includes: a first insulating plate; a second insulating plate is arranged above the first insulating plate; a first semiconductor device provided on an upper surface of the first insulating plate; a second semiconductor device provided on a lower surface of the second insulating plate; an insulating substrate including a third insulating plate arranged between the first insulating plate and the second insulating plate, and a conductor provided on the third insulating plate and connected to the first and second semiconductor devices; and sealing resin sealing the first and second semiconductor devices and the insulating substrate, wherein a withstand voltage of the third insulating plate is lower than withstand voltages of the first and second insulating plates.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: May 3, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yusuke Ishiyama
  • Publication number: 20210313253
    Abstract: A semiconductor device includes: a substrate; a semiconductor element arranged on the substrate; a plate-like member electrically connected to the semiconductor element; a first electrode formed on the semiconductor element and joined to the plate-like member with solder; a second electrode formed on the semiconductor element and spaced from the first electrode, and including a metal capable of forming an alloy with the solder; and a metal film formed on the semiconductor element and spaced from the second electrode in a region on the first electrode side as seen from the second electrode, in a two-dimensional view of the semiconductor element as seen from the plate-like member, and including a metal capable of forming an alloy with the solder.
    Type: Application
    Filed: September 24, 2019
    Publication date: October 7, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Shohei OGAWA, Junji FUJINO, Yusuke ISHIYAMA, Isao OSHIMA, Takumi SHIGEMOTO
  • Publication number: 20210193611
    Abstract: A semiconductor device includes an insulating substrate formed by integrating a ceramic base plate and a cooling fin; a multiple of plate interconnection members; and a plurality of semiconductor elements. The one faces of the semiconductor elements are bonded to the ceramic base plate of the insulating substrate with a chip-bottom solder, and the other faces thereof are bonded to the plate-interconnection members with a chip-top solder so that plate interconnection members correspond respectively to the semiconductor elements. The chip-bottom solder and the chip-top solder both contain mainly Sn and 0.3-3 wt. % Ag and 0.5-1 wt. % Cu. This allows the semiconductor device to be reduced in size without impairing heat dissipation.
    Type: Application
    Filed: November 29, 2018
    Publication date: June 24, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Shohei OGAWA, Junji FUJINO, Satoru ISHIKAWA, Takumi SHIGEMOTO, Yusuke ISHIYAMA
  • Publication number: 20210066175
    Abstract: A semiconductor module includes: an insulated circuit board; a semiconductor device mounted on the insulated circuit board; a printed wiring board arranged above the insulated circuit board and the semiconductor device and having a through-hole; a metal pile having a lower end bonded to an upper surface of the semiconductor device and a cylindrical portion penetrating through the through-hole and bonded to the printed wiring board; a case surrounding the insulated circuit board, the semiconductor device, the printed wiring board and the metal pile; and a sealing material sealing an inside of the case.
    Type: Application
    Filed: April 9, 2020
    Publication date: March 4, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Satoshi KONDO, Hidetoshi ISHIBASHI, Hiroshi YOSHIDA, Nobuhiro ASAJI, Junji FUJINO, Yusuke ISHIYAMA, Hodaka ROKUBUICHI
  • Publication number: 20200335445
    Abstract: A semiconductor module includes: a first insulating plate; a second insulating plate is arranged above the first insulating plate; a first semiconductor device provided on an upper surface of the first insulating plate; a second semiconductor device provided on a lower surface of the second insulating plate; an insulating substrate including a third insulating plate arranged between the first insulating plate and the second insulating plate, and a conductor provided on the third insulating plate and connected to the first and second semiconductor devices; and sealing resin sealing the first and second semiconductor devices and the insulating substrate, wherein a withstand voltage of the third insulating plate is lower than withstand voltages of the first and second insulating plates.
    Type: Application
    Filed: October 24, 2019
    Publication date: October 22, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventor: Yusuke ISHIYAMA
  • Patent number: 10734300
    Abstract: A semiconductor device according to the present invention includes the following: a conductive layer disposed on an insulating substrate; a first semiconductor element and a second semiconductor element that are joined on an opposite surface of the conductive layer opposite from the insulating substrate, with a gap the first semiconductor element and the second semiconductor element; an electrode joined on an opposite surface of the first semiconductor element opposite from the conductive layer, and an opposite surface of the second semiconductor element opposite from the conductive layer, so as to extend over the gap; and resin sealing the conductive layer, the first semiconductor element, the second semiconductor element, and the electrode. The conductive layer has a recess pattern that is disposed on a surface being opposite from the insulating substrate and facing the gap, the recess pattern extending along the gap.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: August 4, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Mitsugu Tanaka, Yusuke Ishiyama, Akitoshi Shirao
  • Publication number: 20190295915
    Abstract: A semiconductor device according to the present invention includes the following: a conductive layer disposed on an insulating substrate; a first semiconductor element and a second semiconductor element that are joined on an opposite surface of the conductive layer opposite from the insulating substrate, with a gap the first semiconductor element and the second semiconductor element; an electrode joined on an opposite surface of the first semiconductor element opposite from the conductive layer, and an opposite surface of the second semiconductor element opposite from the conductive layer, so as to extend over the gap; and resin sealing the conductive layer, the first semiconductor element, the second semiconductor element, and the electrode. The conductive layer has a recess pattern that is disposed on a surface being opposite from the insulating substrate and facing the gap, the recess pattern extending along the gap.
    Type: Application
    Filed: December 8, 2016
    Publication date: September 26, 2019
    Inventors: Mitsugu TANAKA, Yusuke ISHIYAMA, Akitoshi SHIRAO
  • Patent number: 9917064
    Abstract: A semiconductor device includes a semiconductor element having a lower surface bonded to an insulating substrate side, and a plate-shaped lead terminal bonded to an upper surface of the semiconductor element, and having a horizontally extending portion. The horizontally extending portion in the lead terminal is bonded to the semiconductor element and includes a linearly extending portion in a planar view. The semiconductor device further includes a sealing resin that seals the semiconductor element together with the linearly extending portion in the lead terminal. A linear expansion coefficient of the sealing resin shows a value intermediate between a linear expansion coefficient of the lead terminal and a linear expansion coefficient of the semiconductor element, and the lead terminal includes a recess or a projection to horizontally and partially separate the linearly extending portion into parts.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: March 13, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yusuke Ishiyama, Yuji Imoto, Junji Fujino, Shinsuke Asada, Mikio Ishihara
  • Patent number: 9888617
    Abstract: Provided is a semiconductor device having a small footprint, where the semiconductor device includes multiple power modules and a cooling structure for these power modules. The semiconductor device includes: a first power module on a first top plate of a coolant jacket; and a second power module on a second top plate of the coolant jacket, where the second top plate face the first top plate. The coolant jacket includes a first fin in contact with the first top plate in a passage, and a second fin in contact with the second top plate in the passage. The power modules face each other through the top plates and the fins.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: February 6, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yusuke Ishiyama, Yuji Imoto
  • Publication number: 20170213779
    Abstract: Provided is a semiconductor device having a small footprint, where the semiconductor device includes multiple power modules and a cooling structure for these power modules. The semiconductor device includes: a first power module on a first top plate of a coolant jacket; and a second power module on a second top plate of the coolant jacket, where the second top plate face the first top plate. The coolant jacket includes a first fin in contact with the first top plate in a passage, and a second fin in contact with the second top plate in the passage. The power modules face each other through the top plates and the fins.
    Type: Application
    Filed: August 8, 2016
    Publication date: July 27, 2017
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yusuke ISHIYAMA, Yuji IMOTO
  • Patent number: 9698091
    Abstract: A power semiconductor device includes an insulating substrate, a semiconductor element, a case, and a wiring member. The case forms a container body having a bottom surface defined by a surface of the insulating substrate, to which said semiconductor element is bonded. The wiring member has a bonding portion positioned above an upper surface electrode of the semiconductor element. The bonding portion of the wiring member is provided with a projection portion projecting toward the upper surface electrode of the semiconductor element and bonded to the upper surface electrode with a solder, and a through hole passing through the bonding portion in a thickness direction through the projection portion.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: July 4, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinsuke Asada, Naoki Yoshimatsu, Yuji Imoto, Yusuke Ishiyama, Junji Fujino
  • Patent number: 9691730
    Abstract: A semiconductor device according to the present invention includes an insulating substrate having a circuit pattern, semiconductor elements bonded on the circuit pattern with a brazing material, and a wiring terminal bonded with a brazing material on an electrode provided on each of the semiconductor elements on an opposite side of the circuit pattern, in which a part of the wiring terminal is in contact with the insulating substrate, and insulated from the circuit pattern.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: June 27, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naoki Yoshimatsu, Yusuke Ishiyama, Taketoshi Shikano, Yuji Imoto, Junji Fujino, Shinsuke Asada
  • Publication number: 20160111379
    Abstract: A semiconductor device includes a semiconductor element having a lower surface bonded to an insulating substrate side, and a plate-shaped lead terminal bonded to an upper surface of the semiconductor element, and having a horizontally extending portion. The horizontally extending portion in the lead terminal is bonded to the semiconductor element and includes a linearly extending portion in a planar view. The semiconductor device further includes a sealing resin that seals the semiconductor element together with the linearly extending portion in the lead terminal. A linear expansion coefficient of the sealing resin shows a value intermediate between a linear expansion coefficient of the lead terminal and a linear expansion coefficient of the semiconductor element, and the lead terminal includes a recess or a projection to horizontally and partially separate the linearly extending portion into parts.
    Type: Application
    Filed: July 2, 2015
    Publication date: April 21, 2016
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yusuke ISHIYAMA, Yuji IMOTO, Junji FUJINO, Shinsuke ASADA, Mikio ISHIHARA
  • Publication number: 20160104651
    Abstract: A power semiconductor device includes an insulating substrate, a semiconductor element, a case, and a wiring member. The case forms a container body having a bottom surface defined by a surface of the insulating substrate, to which said semiconductor element is bonded. The wiring member has a bonding portion positioned above an upper surface electrode of the semiconductor element. The bonding portion of the wiring member is provided with a projection portion projecting toward the upper surface electrode of the semiconductor element and bonded to the upper surface electrode with a solder, and a through hole passing through the bonding portion in a thickness direction through the projection portion.
    Type: Application
    Filed: June 29, 2015
    Publication date: April 14, 2016
    Applicant: Mitsubishi Electric Corporation
    Inventors: Shinsuke ASADA, Naoki YOSHIMATSU, Yuji IMOTO, Yusuke ISHIYAMA, Junji FUJINO