Patents by Inventor Yusuke Kanno

Yusuke Kanno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210003548
    Abstract: An electrochemical measurement apparatus includes: a tank containing electrolytic solution and a sample that generates or consumes measurement target substances in the electrolytic solution; a plurality of uniformly mixed working electrodes; and a counter electrode; the apparatus adapted to simultaneously apply a voltage between each of the working electrodes and the counter electrode; and the apparatus configured to measure a current that flows between each of the working electrodes and the counter electrode; wherein any two working electrode groups are mutually different in at least any of the determined voltage, presence/absence of a molecular modification of an electrode surface, and a species of the molecular modification; and whereby a distribution in measurement area of the currents that flow through the working electrodes is acquired.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 7, 2021
    Applicants: TOHOKU UNIVERSITY, JAPAN AVIATION ELECTRONICS INDUSTRY, LIMITED
    Inventors: Kosuke INO, Yusuke KANNO, Tomokazu MATSUE, Kumi INOUE, Ryota KUNIKATA, Hiroyuki HAYASHI, Atsushi SUDA
  • Publication number: 20210003549
    Abstract: An electrochemical measurement apparatus includes: a tank containing electrolytic solution and a sample that generates or consumes measurement target substances in the electrolytic solution; a plurality of uniformly mixed working electrodes; and a counter electrode; the apparatus adapted to simultaneously apply a voltage between each of the working electrodes and the counter electrode; and the apparatus configured to measure a current that flows between each of the working electrodes and the counter electrode; wherein any two working electrode groups are mutually different in at least any of the determined voltage, presence/absence of a molecular modification of an electrode surface, and a species of the molecular modification; and whereby a distribution in measurement area of the currents that flow through the working electrodes is acquired.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 7, 2021
    Applicants: TOHOKU UNIVERSITY, JAPAN AVIATION ELECTRONICS INDUSTRY, LIMITED
    Inventors: Kosuke INO, Yusuke KANNO, Tomokazu MATSUE, Kumi INOUE, Ryota KUNIKATA, Hiroyuki HAYASHI, Atsushi SUDA
  • Publication number: 20200384782
    Abstract: A printing apparatus includes a transport roller configured to transport a print medium in a transport direction, a print head configured to print on the print medium, a platen having first suction arrays each including at least a first suction hole having a first diameter and second suction arrays each including at least a second suction hole having a second diameter that is different from the first diameter, the first suction arrays and the second suction arrays being alternately arranged in a direction intersecting the transport direction, a suction fan configured to suck the print medium through frame portions each having one first suction array and one second suction array, and a shutter mechanism configured to open or close the frame portions stepwise.
    Type: Application
    Filed: June 8, 2020
    Publication date: December 10, 2020
    Inventors: Yusuke KANNO, Hiroyuki ENDO
  • Publication number: 20200376859
    Abstract: A printer for printing on rolled paper includes an air pressure sensor that detects air pressure, a platen that has a suction hole and is installed on a transport path of the rolled paper, a suction fan that sucks the rolled paper via the suction hole, and a control section that performs control for changing a rotation speed of the suction fan according to a detection result of the air pressure sensor.
    Type: Application
    Filed: May 27, 2020
    Publication date: December 3, 2020
    Inventors: Yusuke KANNO, Hiroyuki ENDO
  • Publication number: 20200295355
    Abstract: A composite material includes vanadium lithium phosphate, and a conductive carbon. an amount of the conductive carbon is 2.5 mass % or more and 7.5 mass % or less.
    Type: Application
    Filed: March 10, 2020
    Publication date: September 17, 2020
    Applicant: Ricoh Company, Ltd.
    Inventors: Yusuke KANNO, Hideo YANAGITA, Satoshi NAKAJIMA, Eiko SUZUKI, Anna HIROWATARI
  • Patent number: 10684691
    Abstract: According to one embodiment, a gesture detection supporting system for an X-ray diagnosis includes memory circuitry, a sensor, processing circuitry and an attaching instrument. The memory circuitry stores an operation content of an X-ray diagnostic apparatus. The operation content is related to a gesture by a user. The sensor senses a gesture. The processing circuitry detects the gesture, based on an output from the sensor; acquire the operation content of the X-ray diagnostic apparatus, from the memory circuitry, based on a detection result of the gesture; and output operation information to the X-ray diagnostic apparatus, based on the operation content. The attaching instrument attaches the sensor to a ceiling of an examination room, an arm for driving an X-ray tube and an X-ray detector, an intravenous drip stand, an injector of a contrast agent, an X-ray protective board and/or a display for displaying an X-ray image.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: June 16, 2020
    Assignee: Canon Medical Systems Corporation
    Inventors: Yoshiyasu Hayashi, Yuichiro Watanabe, Jun Sakakibara, Ko Fuchigami, Yusuke Kanno, Masaki Akiyama
  • Publication number: 20200006384
    Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
    Type: Application
    Filed: September 10, 2019
    Publication date: January 2, 2020
    Inventors: Yusuke KANNO, Hiroyuki MIZUNO, Yoshihiko YASU, Kenji HIROSE, Takahiro IRITA
  • Patent number: 10506997
    Abstract: An X-ray diagnostic apparatus includes a display, a holding device, bed device, a gesture detecting device and a processing circuitry. The holding device includes an X-ray irradiator, an X-ray detector, and a supporter that supports the X-ray irradiator and the X-ray detector. The bed device is available to place an object on. The gesture detecting device recognizes a gesture of a person. The processing circuitry identifies a state of the X-ray diagnostic apparatus based on at least one of the display, the X-ray irradiator, the X-ray detector, the holding device and the bed device, determines an operation detail based on a combination of the identified state and the recognized gesture, and operates at least one of the display, the holding device, the bed device, a speaker and a room light according to the determined operation detail.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: December 17, 2019
    Assignee: CANON MEDICAL SYSTEMS CORPORATION
    Inventors: Ko Fuchigami, Jun Sakakibara, Yuichiro Watanabe, Yusuke Kanno
  • Patent number: 10446581
    Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: October 15, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Takahiro Irita
  • Patent number: 10438383
    Abstract: The present invention includes a drawing data generating unit, a variation pattern that varies at regular intervals to be displayed, a display unit that displays drawing data, and a comparator that compares whether input signals are coincident, and the drawing data generating unit includes a receiver that receives data from a higher-level device, a drawing control unit that converts the data received from the higher-level device to drawing data, and a drawing memory that stores the drawing data. The drawing data generating unit and the variation pattern are redundantly configured, and the variation pattern is input to the drawing data generating unit. One output signal of the drawing data generating unit regarding drawing data including the variation pattern is transmitted to the display unit, a plurality of output signals from the drawing data generating unit are input to the comparator, and the comparator outputs a comparison result as a detection signal outside.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: October 8, 2019
    Assignee: HITACHI, LTD.
    Inventors: Tadanobu Toba, Takumi Uezono, Yusuke Kanno, Masahiro Shiraishi, Hideo Harada, Satoru Akasaka
  • Patent number: 10339242
    Abstract: Provided is a technology capable of reducing the number of resources necessary for logic implementation in a control device. A semiconductor LSI design device generates a combinational circuit configured with functional blocks defined by a functional block library from an application specification, allocates an operation order of each functional block in the combinational circuit under a condition for starting an operation of a functional block connected to an input pin after ending the operation, converts into a sequence circuit which uses the functional block twice or more in a time division manner, extracts the operation order at a time of execution of the sequential circuit, and determines whether the operation order allocated to the combinational circuit coincide with the extracted operation execution order.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: July 2, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Takumi Uezono, Tadanobu Toba, Yusuke Kanno, Masahiro Shiraishi, Hideo Harada, Satoshi Nishikawa, Toru Motoya
  • Patent number: 10095570
    Abstract: The present invention aims to provide a programmable device with a configuration memory that can hold the state of the occurrence abnormal situation that is difficult to assume such as a failure occurring in the programmable device due to the terrestrial radiation of the configuration memory, even during power off, in order to improve the reproducibility in device testing based on the held error information. The programmable device with the configuration memory includes: an error detection section for detecting an error in the configuration memory, and outputting the detected error as well as an address in which the error occurred, as error information; and an error information holding section provided with a non-volatile memory to store the output error information.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: October 9, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Tadanobu Toba, Kenichi Shimbo, Yusuke Kanno, Nobuyasu Kanekawa, Kotaro Shimamura, Hiromichi Yamada
  • Publication number: 20180286885
    Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
    Type: Application
    Filed: June 6, 2018
    Publication date: October 4, 2018
    Inventors: Yusuke KANNO, Hiroyuki MIZUNO, Yoshihiko YASU, Kenji HIROSE, Takahiro IRITA
  • Publication number: 20180260687
    Abstract: Efficient learning of a neural network can be performed. A plurality of DNNs are hierarchically configured, and data of a hidden layer of a DNN of a first hierarchy machine learning/recognizing device is used as input data of a DNN of a second hierarchy machine learning/recognizing device.
    Type: Application
    Filed: April 26, 2016
    Publication date: September 13, 2018
    Inventors: Yusuke KANNO, Takeshi SAKATA, Shigeru NAKAHARA
  • Patent number: 10046583
    Abstract: Roll paper for printing maintains high bending resistance at the perforations without impairing the ease of separation at the perforation. The paper has perforations 15A, 25A formed across the width of the paper at a specific interval lengthwise, and the perforation 15A, 25A have either a sawtooth shape or a wave shape. The roll paper also has a liner 11, and a plurality of labels 12 affixed by adhesive 13 at an even interval along the length of the liner 11. The perforation 15A, 25A are formed in the liner 11 between two adjacent labels 12.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: August 14, 2018
    Assignee: Seiko Epson Corporation
    Inventors: Hiroyuki Endo, Yusuke Kanno
  • Patent number: 10033357
    Abstract: Provided is a semiconductor device capable of reducing a penalty associated with ensuring reliability. The semiconductor device includes a latch circuit which has input/output paths of three systems or more independent from each other. The latch circuit includes a plurality of storage elements STE1 to STE3 which are provided on the input/output paths of the three systems or more, respectively, and hold input data in synchronization with a clock signal. At least one storage element (for example, STE1) of the plurality of storage elements STE1 to STE3 includes a majority decision unit (for example, 81a) executing a majority decision using data from the storage elements provided on other input/output paths different from the input/output path thereof and outputs data in which a result of the majority decision is reflected.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: July 24, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Yusuke Kanno, Takeshi Sakata, Nobuyasu Kanekawa
  • Patent number: 10014320
    Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: July 3, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Takahiro Irita
  • Publication number: 20170364610
    Abstract: Provided is a technology capable of reducing the number of resources necessary for logic implementation in a control device. A semiconductor LSI design device generates a combinational circuit configured with functional blocks defined by a functional block library from an application specification, allocates an operation order of each functional block in the combinational circuit under a condition for starting an operation of a functional block connected to an input pin after ending the operation, converts into a sequence circuit which uses the functional block twice or more in a time division manner, extracts the operation order at a time of execution of the sequential circuit, and determines whether the operation order allocated to the combinational circuit coincide with the extracted operation execution order.
    Type: Application
    Filed: June 14, 2017
    Publication date: December 21, 2017
    Inventors: Takumi UEZONO, Tadanobu TOBA, Yusuke KANNO, Masahiro SHIRAISHI, Hideo HARADA, Satoshi NISHIKAWA, Toru MOTOYA
  • Publication number: 20170357567
    Abstract: A verification method for an application logic provided with one or more macro logics configured to perform a predetermined operation, a macro operation control unit configured to instruct the one or more macro logics to start the operation to cause the one or more macro logics to perform the operation, and an operation data storage area configured to store data. In the application logic, static verification by property description of a formal verification language is performed for each of the one or more macro logic, the macro operation control unit, and the operation data storage area, and dynamic verification by simulation is further performed for at least one of the one or more macro logics.
    Type: Application
    Filed: June 13, 2017
    Publication date: December 14, 2017
    Applicant: HITACHI, LTD.
    Inventors: Toru MOTOYA, Masahiro SHIRAISHI, Satoshi NISHIKAWA, Keisuke YAMAMOTO, Tadanobu TOBA, Takumi UEZONO, Hideo HARADA, Yusuke KANNO
  • Publication number: 20170336384
    Abstract: In an electrochemical imaging method of, by applying voltages between working electrodes arranged in a measurement area and a counter electrode and causing the working electrodes to perform a redox reaction by giving and reception of electrons to and from a plurality of measurement target substances generated or consumed by a sample in an electrolytic solution to measure currents that flow through the individual electrodes, imaging images of density distributions of the measurement target substances based on distributions of the currents in the measurement area, the working electrodes are arranged in the measurement area in a manner of being arranged uniformly in each of a plurality of working electrode groups, each of the working electrode groups comprising a plurality of working electrodes, and in a manner of being mutually mixed; applied voltages specified for the working electrode groups, respectively, are simultaneously applied between the working electrodes and the counter electrode; any two working ele
    Type: Application
    Filed: May 17, 2017
    Publication date: November 23, 2017
    Applicants: TOHOKU UNIVERSITY, JAPAN AVIATION ELECTRONICS INDUSTRY, LIMITED
    Inventors: Kosuke INO, Yusuke KANNO, Tomokazu MATSUE, Kumi INOUE, Ryota KUNIKATA, Hiroyuki HAYASHI, Atsushi SUDA