Patents by Inventor Yusuke Kawaguchi

Yusuke Kawaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11489070
    Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first to third semiconductor regions, a structure body, and a gate electrode. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided selectively on the second semiconductor region. The structure body includes an insulating part and a conductive part. The insulating part is arranged with the third and second semiconductor regions, and a portion of the first semiconductor region. The conductive part is provided in the insulating part. The conductive part includes a portion facing the first semiconductor region. The gate electrode faces the second semiconductor region. The second electrode is provided on the second and third semiconductor regions, and the structure body. The second electrode is electrically connected to the second and third semiconductor regions, and the conductive part.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: November 1, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Takuo Kikuchi, Yusuke Kawaguchi, Tatsuya Nishiwaki, Hidehiko Yabuhara
  • Patent number: 11471842
    Abstract: A liquid-mixing apparatus used in a liquid-mixing method comprises a plurality of supply valves provided to a cylinder. The supply valves make it possible to individually supply a plurality of types of liquids into a retention chamber. Each of the supply valves is configured so as to be switchable between an open state, in which the interior of a supply channel via which a liquid is supplied and the interior of the retention chamber intercommunicate, and a closed state, in which communication between the supply channel and the retention chamber is blocked. A piston moves in the direction in which the volume of the retention chamber increases while at least one of the supply valves is in the open state, whereby a liquid is drawn into the storage chamber.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: October 18, 2022
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Hiroki Matsunaga, Masaki Shigekura, Masayuki Yamaguchi, Takashi Wakimoto, Yusuke Kawaguchi, Satoshi Sakamoto
  • Publication number: 20220302288
    Abstract: This semiconductor device includes: a semiconductor layer having a first face and a second face, the semiconductor layer including a first trench and a second trench in a first face side; a first gate electrode in the first trench; a first conductive layer in the first trench and between the first gate electrode and the second face, the first conductive layer being electrically separated from the first gate electrode; a second gate electrode in the second trench; a second conductive layer in the second trench and between the second gate electrode and the second face; a first electrode on a the first face side; a second electrode on a side of the second face; a first gate electrode pad being electrically connected to the first gate electrode; and a second gate electrode pad being electrically connected to the second gate electrode.
    Type: Application
    Filed: September 13, 2021
    Publication date: September 22, 2022
    Inventors: Norio YASUHARA, Yoko IWAKAJI, Yusuke KAWAGUCHI, Daiki YOSHIKAWA, Kenichi MATSUSHITA, Shoko HANAGATA, Tomoko MATSUDAI, Hiroko ITOKAZU, Keiko KAWAMURA
  • Patent number: 11305997
    Abstract: Applicability to a composite material with high purity and high strength, and a material requiring high conductivity or high thermal conductivity is enhanced. The present invention relates to a multi-walled carbon nanotube having two or more tubes of a graphene sheet where carbon atoms are arranged in a hexagonal honeycomb form, coaxially, wherein a diameter of an outermost wall based on observation of an image by a transmission electron microscope is 3 nm or more and 15 nm or less, and a length based on observation of an image of a scanning electron microscope is 1.0 mm or more, an aggregate of multi-walled carbon nanotubes and a method for preparing the multi-walled carbon nanotube.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: April 19, 2022
    Assignee: TPR CO., LTD.
    Inventors: Toshiaki Shimizu, Shinpei Teshima, Yasuhiko Okamura, Yusuke Kawaguchi, Kazuki Otomo, Yuta Koguchi, Katsuhito Suzuki, Yoshio Bando
  • Publication number: 20210288178
    Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first to third semiconductor regions, a structure body, and a gate electrode. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided selectively on the second semiconductor region. The structure body includes an insulating part and a conductive part. The insulating part is arranged with the third and second semiconductor regions, and a portion of the first semiconductor region. The conductive part is provided in the insulating part. The conductive part includes a portion facing the first semiconductor region. The gate electrode faces the second semiconductor region. The second electrode is provided on the second and third semiconductor regions, and the structure body. The second electrode is electrically connected to the second and third semiconductor regions, and the conductive part.
    Type: Application
    Filed: March 8, 2021
    Publication date: September 16, 2021
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Takuo KIKUCHI, Yusuke KAWAGUCHI, Tatsuya NISHIWAKI, Hidehiko YABUHARA
  • Publication number: 20200339421
    Abstract: Applicability to a composite material with high purity and high strength, and a material requiring high conductivity or high thermal conductivity is enhanced. The present invention relates to a multi-walled carbon nanotube having two or more tubes of a graphene sheet where carbon atoms are arranged in a hexagonal honeycomb form, coaxially, wherein a diameter of an outermost wall based on observation of an image by a transmission electron microscope is 3 nm or more and 15 nm or less, and a length based on observation of an image of a scanning electron microscope is 1.0 mm or more, an aggregate of multi-walled carbon nanotubes and a method for preparing the multi-walled carbon nanotube.
    Type: Application
    Filed: April 16, 2020
    Publication date: October 29, 2020
    Inventors: Toshiaki SHIMIZU, Shinpei TESHIMA, Yasuhiko OKAMURA, Yusuke KAWAGUCHI, Kazuki OTOMO, Yuta KOGUCHI, Katsuhito SUZUKI, Yoshio BANDO
  • Patent number: 10763359
    Abstract: A semiconductor device includes a first conductivity type first semiconductor region, a second semiconductor region on the first semiconductor region, a third semiconductor region on the second semiconductor region, a first insulating portion extending inwardly of, and surrounded by, the first semiconductor region, a gate electrode extending inwardly of the first insulating portion and spaced from the second semiconductor region in a second direction that intersects a first direction extending from the first semiconductor region to the second semiconductor region, by the first insulating portion, and a first electrode including a portion spaced from the first semiconductor region in the second direction by the first insulating portion, and surrounded by the first insulating portion and the gate electrode.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: September 1, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shunsuke Katoh, Yusuke Kawaguchi
  • Publication number: 20200230630
    Abstract: A painting system used in a painting method in which a plurality of colors of paint supplied from a paint supply device are mixed and toned with a mixing device and applied to a workpiece, the painting system comprising a storage unit that can store the paint that is mixed and toned with the mixing device, and a cleaning unit that can clean the mixing device. When applying the paint in the storage unit to the workpiece, the cleaning unit cleans the mixing device.
    Type: Application
    Filed: August 1, 2018
    Publication date: July 23, 2020
    Inventors: Hiroki Matsunaga, Masaki Shigekura, Masayuki Yamaguchi, Takashi Wakimoto, Yusuke Kawaguchi, Satoshi Sakamoto
  • Publication number: 20200230560
    Abstract: A liquid-mixing apparatus used in a liquid-mixing method comprises a plurality of supply valves provided to a cylinder. The supply valves make it possible to individually supply a plurality of types of liquids into a retention chamber. Each of the supply valves is configured so as to be switchable between an open state, in which the interior of a supply channel via which a liquid is supplied and the interior of the retention chamber intercommunicate, and a closed state, in which communication between the supply channel and the retention chamber is blocked. A piston moves in the direction in which the volume of the retention chamber increases while at least one of the supply valves is in the open state, whereby a liquid is drawn into the storage chamber.
    Type: Application
    Filed: August 1, 2018
    Publication date: July 23, 2020
    Inventors: Hiroki Matsunaga, Masaki Shigekura, Masayuki Yamaguchi, Takashi Wakimoto, Yusuke Kawaguchi, Satoshi Sakamoto
  • Patent number: 10453957
    Abstract: A semiconductor device includes a first semiconductor region, a second semiconductor region between a first gate electrode and a second gate electrode that is disposed apart from the first gate electrode in a first direction, third and fourth semiconductor regions provided on respective portions of the second semiconductor region, an insulating region provided between the third semiconductor region and the fourth semiconductor region, and an electrode provided on the third semiconductor region and the fourth semiconductor region and electrically connected to the third semiconductor region and the fourth semiconductor region. The fourth semiconductor region is parallel to the third semiconductor region in a direction intersecting the first direction. The fourth semiconductor region has an impurity concentration higher than that of the second semiconductor region.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: October 22, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenya Kobayashi, Kenji Maeyama, Koji Matsuo, Yusuke Kawaguchi
  • Publication number: 20190123197
    Abstract: A semiconductor device includes a first conductivity type first semiconductor region, a second semiconductor region on the first semiconductor region, a third semiconductor region on the second semiconductor region, a first insulating portion extending inwardly of, and surrounded by, the first semiconductor region, a gate electrode extending inwardly of the first insulating portion and spaced from the second semiconductor region in a second direction that intersects a first direction extending from the first semiconductor region to the second semiconductor region, by the first insulating portion, and a first electrode including a portion spaced from the first semiconductor region in the second direction by the first insulating portion, and surrounded by the first insulating portion and the gate electrode.
    Type: Application
    Filed: December 21, 2018
    Publication date: April 25, 2019
    Inventors: Shunsuke KATOH, Yusuke KAWAGUCHI
  • Patent number: 10236377
    Abstract: A semiconductor device includes a first conductivity type first semiconductor region, a second semiconductor region on the first semiconductor region, a third semiconductor region on the second semiconductor region, a first insulating portion extending inwardly of, and surrounded by, the first semiconductor region, a gate electrode extending inwardly of the first insulating portion and spaced from the second semiconductor region in a second direction that intersects a first direction extending from the first semiconductor region to the second semiconductor region, by the first insulating portion, and a first electrode including a portion spaced from the first semiconductor region in the second direction by the first insulating portion, and surrounded by the first insulating portion and the gate electrode.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: March 19, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shunsuke Katoh, Yusuke Kawaguchi
  • Publication number: 20180269008
    Abstract: To transfer slurry without a binder smoothly in each transition between a dewatering process, a water squeezing process, and a drying process during formation of the slurry into a sheet-like shape through these processes. A dewatering process unit P1 conveys slurry while removing moisture in the slurry. A water squeezing process unit P2 conveys the resultant slurry while squeezing water from the slurry by rolling the slurry. A drying process unit P3 conveys the resultant slurry while drying the slurry by heating the slurry. The conveyance speed of the slurry in the water squeezing process is lower than the conveyance speed of the slurry in the dewatering process. The conveyance speed of the slurry in the drying process is lower than the conveyance speed of the slurry in the water squeezing process.
    Type: Application
    Filed: March 14, 2018
    Publication date: September 20, 2018
    Inventors: Yusuke Kawaguchi, Toshiaki Shimizu, Toyokazu Kumazawa, Satoshi Oyama, Hiromu Kobori, Keisuke Ota, Shinpei Teshima, Kentaro Matsunaga
  • Patent number: 10020123
    Abstract: Provided is a carbon fiber membrane which is inexpensive and can sufficiently increase the electric capacity per mass. The carbon fiber membrane includes only carbon nanotubes and carbon material other than carbon nanotubes, and the carbon nanotubes each having a fiber length of 30 to 500 ?m are contained in an amount of 3% by mass or more to less than 100% by mass with respect to the total amount.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: July 10, 2018
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Yusuke Kawaguchi, Satoshi Aoki, Toshiaki Shimizu
  • Publication number: 20180083137
    Abstract: A semiconductor device includes a first semiconductor region, a second semiconductor region between a first gate electrode and a second gate electrode that is disposed apart from the first gate electrode in a first direction, third and fourth semiconductor regions provided on respective portions of the second semiconductor region, an insulating region provided between the third semiconductor region and the fourth semiconductor region, and an electrode provided on the third semiconductor region and the fourth semiconductor region and electrically connected to the third semiconductor region and the fourth semiconductor region. The fourth semiconductor region is parallel to the third semiconductor region in a direction intersecting the first direction. The fourth semiconductor region has an impurity concentration higher than that of the second semiconductor region.
    Type: Application
    Filed: March 3, 2017
    Publication date: March 22, 2018
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenya KOBAYASHI, Kenji MAEYAMA, Koji MATSUO, Yusuke KAWAGUCHI
  • Publication number: 20170263768
    Abstract: A semiconductor device includes a first conductivity type first semiconductor region, a second semiconductor region on the first semiconductor region, a third semiconductor region on the second semiconductor region, a first insulating portion extending inwardly of, and surrounded by, the first semiconductor region, a gate electrode extending inwardly of the first insulating portion and spaced from the second semiconductor region in a second direction that intersects a first direction extending from the first semiconductor region to the second semiconductor region, by the first insulating portion, and a first electrode including a portion spaced from the first semiconductor region in the second direction by the first insulating portion, and surrounded by the first insulating portion and the gate electrode.
    Type: Application
    Filed: August 30, 2016
    Publication date: September 14, 2017
    Inventors: Shunsuke KATOH, Yusuke KAWAGUCHI
  • Patent number: 9614072
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a first electrode, a second electrode, a third electrode, a first insulation region, a second insulation region, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a fourth semiconductor region of the second conductivity type, and a fourth electrode. The second electrode includes first portions and a second portion. The second portion extends in a first direction. The first portions extend in a direction away from the second portion. The second portion is between the first portions and the first electrode in a second direction. The fourth semiconductor region is positioned between adjacent first electrode portions in the first direction.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: April 4, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yusuke Kawaguchi
  • Publication number: 20160380047
    Abstract: A semiconductor device includes a first electrode, a first semiconductor layer of a first conductivity type located on the first electrode, a second semiconductor layer of a second conductivity type located on the first semiconductor layer, a third semiconductor layer of the first conductivity type located on a portion of the second semiconductor layer, a second electrode located in the first semiconductor layer, the second semiconductor layer and the third semiconductor layer, the second electrode extending along and around an outer edge of the first semiconductor layer, and spaced from the second semiconductor layer by an insulating film, a wiring located on the third semiconductor layer and connected to the second electrode, and a third electrode connected to the second semiconductor layer and the third semiconductor layer.
    Type: Application
    Filed: February 29, 2016
    Publication date: December 29, 2016
    Inventors: Takuma HARA, Yusuke KAWAGUCHI
  • Patent number: RE46204
    Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a semiconductor region provided in the semiconductor substrate; a first trench formed in the semiconductor region; a second trench formed in the semiconductor substrate; a trench gate electrode provided in the first trench; and a trench source electrode provided in the second trench. The trench source electrode is shaped like a stripe and connected to the source electrode through its longitudinal portion.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: November 15, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yusuke Kawaguchi, Miwako Akiyama, Yoshihiro Yamaguchi, Nobuyuki Sato, Shigeaki Hayase
  • Patent number: RE46311
    Abstract: According to one embodiment, a semiconductor device, includes an element unit including a vertical-type MOSFET, the vertical-type MOSFET in including a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer sequentially stacked in order, an impurity concentration of the second semiconductor layer being lower than the first semiconductor layer, an insulator covering inner surfaces of a plurality of trenches, the adjacent trenches being provided with a first interval in between, and a diode unit including basically with the units of the element unit, the adjacent trenches being provided with a second interval in between, the second interval being larger than the first interval.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: February 14, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yusuke Kawaguchi