Patents by Inventor Yusuke Kumazaki

Yusuke Kumazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250096180
    Abstract: A semiconductor device includes a semiconductor element; an interconnect layer provided on a first surface side of the semiconductor element, the interconnect layer including an interconnect connected to the semiconductor element and an insulating layer covering the interconnect; and a cavity provided between the first surface of the semiconductor element and the interconnect layer.
    Type: Application
    Filed: September 3, 2024
    Publication date: March 20, 2025
    Applicant: Fujitsu Limited
    Inventors: Shirou Ozaki, Yasuhiro Nakasha, Naoya Okamoto, Yusuke Kumazaki, Naoki Hara, Toshihiro Ohki
  • Patent number: 12193151
    Abstract: A high-frequency circuit board includes: a first insulating layer having a first dielectric constant; a first metal layer provided to stack over the first insulating layer; a second insulating layer provided to stack over the first metal layer, and having a second dielectric constant lower than the first dielectric constant; a second metal layer provided to stack over the second insulating layer, on which a compound semiconductor device is mounted; and first vias penetrating the second insulating layer and connecting the first metal layer with the second metal layer.
    Type: Grant
    Filed: January 20, 2023
    Date of Patent: January 7, 2025
    Assignee: Fujitsu Limited
    Inventors: Shirou Ozaki, Naoya Okamoto, Yoshihiro Nakata, Yusuke Kumazaki, Toshihiro Ohki, Naoki Hara
  • Publication number: 20240213360
    Abstract: A semiconductor device has a semiconductor layer including a channel layer containing indium (In), gallium (Ga), and arsenic (As) and an electron supply layer laminated over the channel layer and containing In, Al, and As. A source electrode and a drain electrode are formed on a surface side of the semiconductor layer, and a gate electrode is formed between them. A positively charged insulating film containing aluminum oxide (AlxOy) (y/x<3/2) having oxygen vacancies is formed on the source electrode side from the gate electrode on the surface side of the semiconductor layer. A part of the insulating film may function as a gate insulating film. The density of a two dimensional electron gas (2DEG) in the channel layer on the source electrode side from the gate electrode is relatively higher than that of the 2DEG on the drain electrode side therefrom because of the insulating film.
    Type: Application
    Filed: September 12, 2023
    Publication date: June 27, 2024
    Applicant: Fujitsu Limited
    Inventors: Shirou OZAKI, Naoya OKAMOTO, Yusuke KUMAZAKI, Yasuhiro NAKASHA, Naoki HARA, Toshihiro OHKI
  • Publication number: 20240162340
    Abstract: A semiconductor device includes a semiconductor layer including an electron transit layer and an electron supply layer; a gate electrode, a source electrode and a drain electrode, the gate electrode, the source electrode and the drain electrode being disposed on the semiconductor layer; and a metal film connected to the gate electrode, wherein the semiconductor layer includes an active region, and an inactive region surrounding the active region in plan view, wherein the gate electrode includes, in plan view, a first region overlapping the active region, and two second regions having the first region interposed therebetween, the two second regions both overlapping the inactive region, and wherein the metal film contacts the two second regions.
    Type: Application
    Filed: September 18, 2023
    Publication date: May 16, 2024
    Applicant: Fujitsu Limited
    Inventors: Yusuke KUMAZAKI, Shirou OZAKI, Naoya OKAMOTO, Yasuhiro NAKASHA, Toshihiro OHKI
  • Publication number: 20230354507
    Abstract: A high-frequency circuit board includes: a first insulating layer having a first dielectric constant; a first metal layer provided to stack over the first insulating layer; a second insulating layer provided to stack over the first metal layer, and having a second dielectric constant lower than the first dielectric constant; a second metal layer provided to stack over the second insulating layer, on which a compound semiconductor device is mounted; and first vias penetrating the second insulating layer and connecting the first metal layer with the second metal layer.
    Type: Application
    Filed: January 20, 2023
    Publication date: November 2, 2023
    Applicant: Fujitsu Limited
    Inventors: Shirou OZAKI, Naoya OKAMOTO, Yoshihiro NAKATA, Yusuke Kumazaki, Toshihiro OHKI, Naoki HARA
  • Publication number: 20230317839
    Abstract: A semiconductor device includes a protection film having an opening and covering a semiconductor layer, which is formed on a side of a surface of a substrate, on an opposite side of the substrate. An insulating film containing silicon is used for the protection film. A gate electrode is formed in the opening and on a side of a side surface of the semiconductor layer which faces a direction. An insulating film containing metal element is formed between the side surface of the semiconductor layer and the gate electrode. The exposure of the side surface of the semiconductor layer to a gas for dry etching for forming of the opening is suppressed by the insulating film. Furthermore, contact and a short circuit between the gate electrode and the side surface of the semiconductor layer are suppressed. As a result, deterioration in the performance of the semiconductor device is suppressed.
    Type: Application
    Filed: December 13, 2022
    Publication date: October 5, 2023
    Applicant: Fujitsu Limited
    Inventors: Shirou OZAKI, Naoya Okamoto, Yusuke Kumazaki, Toshihiro Ohki, Naoki Hara
  • Publication number: 20230231045
    Abstract: A semiconductor device includes a channel layer configured to include a first nitride semiconductor containing gallium (Ga) and a first crystal dislocation density, and a barrier layer provided over a first surface side of the channel layer, and configured to include a second nitride semiconductor containing aluminum (Al) and a second crystal dislocation density, wherein the second crystal dislocation density is larger than the first crystal dislocation density.
    Type: Application
    Filed: October 24, 2022
    Publication date: July 20, 2023
    Applicant: Fujitsu Limited
    Inventors: Atsushi YAMADA, Yuichi MINOURA, Yusuke KUMAZAKI
  • Patent number: 11171242
    Abstract: A semiconductor device includes: a semiconductor layer of a first conductivity type formed over a substrate; a plurality of semiconductor nanowires formed of a compound semiconductor of the first conductivity type extending above the semiconductor layer; and a gate electrode formed around the semiconductor nanowires in a connection portion between the semiconductor layer and the semiconductor nanowires.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: November 9, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Kenichi Kawaguchi, Naoya Okamoto, Yusuke Kumazaki, Tsuyoshi Takahashi
  • Patent number: 10964805
    Abstract: A compound semiconductor device includes a compound semiconductor laminate structure including an electron transit layer and an electron supply layer, a gate electrode, a source electrode, and a drain electrode that are formed over the electron supply layer, a first insulating layer of diamond formed between the gate electrode and the drain electrode over the compound semiconductor laminate structure, and a second insulating layer formed between the gate electrode and the source electrode over the compound semiconductor laminate structure, wherein a positive compressive stress is applied from the first insulating layer to the electron supply layer, and a compressive stress from the second insulating layer to the electron supply layer is smaller than the compressive stress from the first insulating layer to the electron supply layer.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: March 30, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Kozo Makiyama, Yuichi Minoura, Yusuke Kumazaki, Toshihiro Ohki, Naoya Okamoto
  • Publication number: 20200365741
    Abstract: A semiconductor device includes: a semiconductor layer of a first conductivity type formed over a substrate; a plurality of semiconductor nanowires formed of a compound semiconductor of the first conductivity type extending above the semiconductor layer; and a gate electrode formed around the semiconductor nanowires in a connection portion between the semiconductor layer and the semiconductor nanowires.
    Type: Application
    Filed: July 31, 2020
    Publication date: November 19, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Kenichi Kawaguchi, Naoya Okamoto, Yusuke Kumazaki, Tsuyoshi Takahashi
  • Publication number: 20200227530
    Abstract: A semiconductor apparatus includes: a substrate; a first semiconductor layer of a nitride semiconductor disposed over the substrate; a second semiconductor layer of a nitride semiconductor disposed over the first semiconductor layer; an insulating film disposed over the second semiconductor layer; a source electrode and a drain electrode that are disposed over the second semiconductor layer; and a gate electrode. The gate electrode includes: a Schottky region disposed over the second semiconductor layer, and a gate field-plate region disposed over the insulating film in the vicinity of the Schottky region, wherein the gate electrode includes a first gate electrode section disposed in the gate field-plate region so as to face the drain electrode, and a second gate electrode section disposed in the Schottky region, and wherein a material constituting the first gate electrode section has a lower work function than a material constituting the second gate electrode section.
    Type: Application
    Filed: December 19, 2019
    Publication date: July 16, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Yusuke Kumazaki, Kozo Makiyama, Toshihiro Ohki, Shirou OZAKI
  • Publication number: 20200058783
    Abstract: A compound semiconductor device includes a compound semiconductor laminate structure including an electron transit layer and an electron supply layer, a gate electrode, a source electrode, and a drain electrode that are formed over the electron supply layer, a first insulating layer of diamond formed between the gate electrode and the drain electrode over the compound semiconductor laminate structure, and a second insulating layer formed between the gate electrode and the source electrode over the compound semiconductor laminate structure, wherein a positive compressive stress is applied from the first insulating layer to the electron supply layer, and a compressive stress from the second insulating layer to the electron supply layer is smaller than the compressive stress from the first insulating layer to the electron supply layer.
    Type: Application
    Filed: August 2, 2019
    Publication date: February 20, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Shirou OZAKI, Kozo Makiyama, Yuichi Minoura, Yusuke Kumazaki, Toshihiro Ohki, NAOYA OKAMOTO
  • Publication number: 20190326404
    Abstract: A semiconductor device includes a substrate, a first semiconductor layer formed over the substrate, the first semiconductor layer being composed of a nitride semiconductor, a second semiconductor layer formed over the first semiconductor layer, the second semiconductor layer being composed of a nitride semiconductor and a gate electrode, a source electrode, and a drain electrode that are formed over the second semiconductor layer, wherein the source electrode including a plurality of protrusions that penetrate into the second semiconductor layer, and the protrusions having a side surface inclined with respect to a surface of the first semiconductor layer.
    Type: Application
    Filed: April 8, 2019
    Publication date: October 24, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Yusuke Kumazaki, Toshihiro Ohki, Kozo Makiyama, Shirou OZAKI, Yuichi Minoura