Patents by Inventor Yusuke Kurasawa
Yusuke Kurasawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10990535Abstract: A storage control apparatus includes a memory to store meta-information associating a position of a logical area with a position of a physical area, and a processor to, when a first data block including data, a check code corresponding to the data, and first information related to a position within the logical area is stored in the physical area, and a second data block including the data, the check code, and second information related to a position within the logical area is written in the logical area, obtain a first position at which the first data block is present in the physical area, based on meta-information of the first data block in the meta-information, associate the first position as a position of the physical area in meta-information of the second data block in the meta-information with the position to which the second data block is written in the logical area.Type: GrantFiled: April 17, 2018Date of Patent: April 27, 2021Assignee: FUJITSU LIMITEDInventors: Naohiro Takeda, Norihide Kubota, Yoshihito Konta, Toshio Kikuchi, Yusuke Kurasawa, Yuji Tanaka, Marino Kajiyama, Yusuke Suzuki, Yoshinari Shinozaki, Takeshi Watanabe
-
Patent number: 10866743Abstract: A storage control device, includes: a memory configured to store meta information and map information, the meta information associates a logical address to identify data from an information processing device which uses a storage with a data block identifier to identify a data block used for an arrangement of the data on the storage and including a header area and a payload area and an index indicating an order of additional writing of the data, the map information associates the data block identifier with a physical identifier indicating a physical position on the storage; and a processor specifies the data block and a write position in a payload area based on the physical identifier and the index, writes the data in the specified data block and performs a write control to write a data unit header including an offset and a data length at a position designated by the index.Type: GrantFiled: January 29, 2019Date of Patent: December 15, 2020Assignee: FUJITSU LIMITEDInventors: Yusuke Suzuki, Yusuke Kurasawa, Norihide Kubota, Yoshihito Konta, Marino Kajiyama, Yuji Tanaka, Toshio Iga, Kazuya Takeda, Takeshi Watanabe
-
Patent number: 10691550Abstract: A storage control apparatus includes a memory configured to store meta-information for associating addresses of a logical area and a physical area with each other, and a processor coupled to the memory and configured to read out first meta-information corresponding to a first logical area from the memory, specify a first address of the physical area corresponding to a copy source address of the data based on the first meta-information, read out second meta-information corresponding to a second logical area that is set as a copy destination of the data in the logical area from the memory, specify a second address of the physical area corresponding to a copy destination address of the data based on the second meta-information, and execute copy of the data by associating the first address and the second address with each other as storage areas of the data.Type: GrantFiled: April 18, 2018Date of Patent: June 23, 2020Assignee: FUJITSU LIMITEDInventors: Yoshinari Shinozaki, Takeshi Watanabe, Norihide Kubota, Yoshihito Konta, Toshio Kikuchi, Naohiro Takeda, Yusuke Kurasawa, Yuji Tanaka, Marino Kajiyama, Yusuke Suzuki
-
Publication number: 20190243563Abstract: A storage control device, includes: a memory configured to store meta information and map information, the meta information associates a logical address to identify data from an information processing device which uses a storage with a data block identifier to identify a data block used for an arrangement of the data on the storage and including a header area and a payload area and an index indicating an order of additional writing of the data, the map information associates the data block identifier with a physical identifier indicating a physical position on the storage; and a processor specifies the data block and a write position in a payload area based on the physical identifier and the index, writes the data in the specified data block and performs a write control to write a data unit header including an offset and a data length at a position designated by the index.Type: ApplicationFiled: January 29, 2019Publication date: August 8, 2019Applicant: FUJITSU LIMITEDInventors: Yusuke Suzuki, Yusuke Kurasawa, Norihide KUBOTA, YOSHIHITO KONTA, Marino Kajiyama, Yuji TANAKA, Toshio IGA, Kazuya Takeda, Takeshi WATANABE
-
Publication number: 20190243758Abstract: A storage control device includes a processor that reads out a group write area, in which data blocks are arranged, from a storage medium and store the group write area in a buffer area. The processor releases a part of the payload area for each data block arranged in the first group write area stored in the first buffer area. The part stores invalid data. The processor performs the garbage collection by performing data refilling. The data refilling is performed by moving valid data stored in the payload to fill up a front by using the released part, and updating an offset included in a header stored in a header area at a position indicated by index information corresponding to the moved valid data without changing the position indicated by the index information corresponding to the moved valid data. The header area is included in the data block.Type: ApplicationFiled: January 9, 2019Publication date: August 8, 2019Applicant: FUJITSU LIMITEDInventors: Kazuya Takeda, Yusuke Kurasawa, Yusuke Suzuki, Norihide KUBOTA, Yuji TANAKA, Toshio IGA, YOSHIHITO KONTA, Marino Kajiyama, Takeshi WATANABE
-
Publication number: 20180307565Abstract: A storage control apparatus includes a memory configured to store meta-information for associating addresses of a logical area and a physical area with each other, and a processor coupled to the memory and configured to read out first meta-information corresponding to a first logical area from the memory, specify a first address of the physical area corresponding to a copy source address of the data based on the first meta-information, read out second meta-information corresponding to a second logical area that is set as a copy destination of the data in the logical area from the memory, specify a second address of the physical area corresponding to a copy destination address of the data based on the second meta-information, and execute copy of the data by associating the first address and the second address with each other as storage areas of the data.Type: ApplicationFiled: April 18, 2018Publication date: October 25, 2018Applicant: FUJITSU LIMITEDInventors: Yoshinari Shinozaki, Takeshi Watanabe, Norihide Kubota, Yoshihito Konta, Toshio Kikuchi, Naohiro Takeda, Yusuke Kurasawa, Yuji Tanaka, Marino Kajiyama, Yusuke Suzuki
-
Publication number: 20180307616Abstract: A storage control apparatus includes a memory to store meta-information associating a position of a logical area with a position of a physical area, and a processor to, when a first data block including data, a check code corresponding to the data, and first information related to a position within the logical area is stored in the physical area, and a second data block including the data, the check code, and second information related to a position within the logical area is written in the logical area, obtain a first position at which the first data block is present in the physical area, based on meta-information of the first data block in the meta-information, associate the first position as a position of the physical area in meta-information of the second data block in the meta-information with the position to which the second data block is written in the logical area.Type: ApplicationFiled: April 17, 2018Publication date: October 25, 2018Applicant: FUJITSU LIMITEDInventors: Naohiro Takeda, Norihide KUBOTA, YOSHIHITO KONTA, Toshio Kikuchi, Yusuke Kurasawa, Yuji TANAKA, Marino Kajiyama, Yusuke Suzuki, YOSHINARI SHINOZAKI, Takeshi WATANABE
-
Publication number: 20180307427Abstract: A storage control apparatus includes a memory, and a processor coupled to the memory and configured to execute a capacity expansion on a storage group including a plurality of storage devices, generate a plurality of first data storage regions in accordance with the number of storage devices within the storage group after the capacity expansion, and execute data rearrangement within the storage group after the capacity expansion for each of the plurality of first data storage regions.Type: ApplicationFiled: April 18, 2018Publication date: October 25, 2018Applicant: FUJITSU LIMITEDInventors: Takeshi WATANABE, YOSHINARI SHINOZAKI, Marino Kajiyama, Toshio Kikuchi, YOSHIHITO KONTA, Norihide KUBOTA, Yusuke Kurasawa, Yusuke Suzuki, Yuji TANAKA, Naohiro Takeda
-
Publication number: 20180307440Abstract: A storage control apparatus configured to control a storage device including a storage medium having a limit of a number of writes, includes a memory, and a processor coupled to the memory and configured to store, in the memory, address conversion information in which a logical address used to identify data by an information processing device using the storage device and a physical address indicating a memory location of the data in the storage medium are associated with each other, and execute a bulk writing of a piece of the address conversion information into the storage medium sequentially.Type: ApplicationFiled: April 10, 2018Publication date: October 25, 2018Applicant: FUJITSU LIMITEDInventors: Naohiro Takeda, Norihide KUBOTA, YOSHIHITO KONTA, Yusuke Kurasawa, Toshio Kikuchi, Yuji TANAKA, Marino Kajiyama, Yusuke Suzuki, YOSHINARI SHINOZAKI, Takeshi WATANABE
-
Publication number: 20180307419Abstract: A storage control apparatus configured to control a storage device including a storage medium with a limited number of writes, includes a memory, and a processor coupled to the memory and configured to record, to the storage medium, address conversion information associating logical addresses by which an information processing apparatus that uses the storage device identifies data with physical addresses indicating positions where the data is stored on the storage medium, and execute garbage collection of the storage medium based on the recorded address conversion information.Type: ApplicationFiled: April 10, 2018Publication date: October 25, 2018Applicant: FUJITSU LIMITEDInventors: Naohiro Takeda, Yusuke Kurasawa, Norihide KUBOTA, YOSHIHITO KONTA, Toshio Kikuchi, Yuji TANAKA, Marino Kajiyama, Yusuke Suzuki, Takeshi WATANABE, YOSHINARI SHINOZAKI
-
Publication number: 20180307615Abstract: A storage control apparatus configured to control a storage device including a storage medium having a limited number of writes, includes a memory, and a processor coupled to the memory and configured to store, in the memory, address conversion information associating logical addresses used for data identification by an information processing apparatus accessing to the storage device, and physical addresses indicating positions where the data is stored on the storage medium, write the data additionally and collectively to the storage medium, and when the data is updated, maintain storing a reference logical address associated with the data before updated and the data before updated on the storage medium.Type: ApplicationFiled: April 13, 2018Publication date: October 25, 2018Applicant: FUJITSU LIMITEDInventors: Naohiro Takeda, Norihide KUBOTA, YOSHIHITO KONTA, Yusuke Kurasawa, Toshio Kikuchi, Yuji TANAKA, Marino Kajiyama, Yusuke Suzuki, YOSHINARI SHINOZAKI, Takeshi WATANABE, Noriyuki Yasu
-
Patent number: 9710319Abstract: An information processing apparatus includes a volatile memory and a nonvolatile memory. An area setting unit sets, upon detection of an abnormality in the information processing apparatus, a work area in a storage area except a collection target area of investigation information used for investigation of a cause of the occurrence of the abnormality, in a storage area of the volatile memory. An information collection unit executes a procedure of collecting investigation information from the volatile memory and storing the same into the nonvolatile memory by using the set work area.Type: GrantFiled: October 7, 2014Date of Patent: July 18, 2017Assignee: FUJITSU LIMITEDInventors: Hiroyuki Hoshino, Kenji Iwasawa, Masako Nishiyama, Yusuke Kurasawa
-
Publication number: 20170075581Abstract: A control device includes a memory device and a processor. The memory device is configured to store therein log information obtained by accumulating logs received from an apparatus. The logs relate to a plurality of processes. The processor is configured to determine on basis of the log information and preset expectation information whether the plurality of processes are normally terminated in a case where the log information includes information indicating that the plurality of processes are normally terminated. The expectation information includes first state information in association with expected state information. The first state information indicates a first state of an object before execution of the plurality of processes. The expected state information indicates an expected state of the object after the execution. The processor is configured to write the log information into a storage device upon determining that the plurality of processes are abnormally terminated.Type: ApplicationFiled: August 23, 2016Publication date: March 16, 2017Applicant: FUJITSU LIMITEDInventors: Kenji IWASAWA, Masakazu SAKAMOTO, Hiroyuki HOSHINO, Yusuke KURASAWA
-
Publication number: 20150121151Abstract: An information processing apparatus includes a volatile memory and a nonvolatile memory. An area setting unit sets, upon detection of an abnormality in the information processing apparatus, a work area in a storage area except a collection target area of investigation information used for investigation of a cause of the occurrence of the abnormality, in a storage area of the volatile memory. An information collection unit executes a procedure of collecting investigation information from the volatile memory and storing the same into the nonvolatile memory by using the set work area.Type: ApplicationFiled: October 7, 2014Publication date: April 30, 2015Inventors: Hiroyuki HOSHINO, Kenji IWASAWA, Masako Nishiyama, Yusuke Kurasawa
-
Patent number: 8713219Abstract: A queue number acquiring unit acquires a command queuing number that is the upper limit of the number of process-waiting instructions that can be stored in each of storages that make up a virtual disk for each storage. A minimum queue number selecting unit selects the minimum value of the command queuing numbers of the storages that make up the virtual disk as a minimum queue number. A queue number setting unit sets the selected minimum queue number as the command queuing number of the virtual disk that includes the storage device of which the command queuing number is selected as the minimum queue number for each virtual disk.Type: GrantFiled: January 26, 2011Date of Patent: April 29, 2014Assignee: Fujitsu LimitedInventors: Toshiaki Takeuchi, Masakazu Sakamoto, Tetsuya Kinoshita, Jun Takeuchi, Atsushi Shinohara, Yusuke Kurasawa
-
Patent number: 8504881Abstract: A switch device includes a memory unit for storing therein an error response for each error event to be sent in response at the time of a failure with respect to a control signal that controls a storage device connected to the switch device, an error response output unit for receiving input of the control signal and sequentially outputting each error response stored in the memory unit, an operation information computing unit for detecting an operation of a calculating device, which is connected to the switch device, corresponding to each error response output by the error response output unit and for obtaining, as operation information, a condition defining the operation of the calculating device upon receiving each error response, and an operation setting unit for setting operation condition at the time of a failure based on the operation information.Type: GrantFiled: February 4, 2011Date of Patent: August 6, 2013Assignee: Fujitsu LimitedInventors: Yusuke Kurasawa, Toshiaki Takeuchi, Masakazu Sakamoto, Tetsuya Kinoshita, Jun Takeuchi, Atsushi Shinohara
-
Patent number: 8443140Abstract: A apparatus for controlling a first storage and a second storage, has a controller for receiving a write command and a read command sent out from a host and for sending out the write command and the read command to the first storage and the second storage, a determining unit for sending out a request corresponding to the write command to the first storage and the second storage, for receiving a first response corresponding to the request from the first storage and a second response corresponding to the request from the second storage, and for determining one of the storages on the basis of each of response times, a first writing unit for writing data into the determined storage, and a second writing unit for writing the data written in the determined storage into the other storage after writing the data into the determined storage by the first writing unit.Type: GrantFiled: June 22, 2010Date of Patent: May 14, 2013Assignee: Fujitsu LimitedInventors: Toshiaki Takeuchi, Masakazu Sakamoto, Tetsuya Kinoshita, Takuya Kurihara, Jun Takeuchi, Atsushi Shinohara, Yusuke Kurasawa
-
Publication number: 20110197091Abstract: A switch device includes a memory unit for storing therein an error response for each error event to be sent in response at the time of a failure with respect to a control signal that controls a storage device connected to the switch device, an error response output unit for receiving input of the control signal and sequentially outputting each error response stored in the memory unit, an operation information computing unit for detecting an operation of a calculating device, which is connected to the switch device, corresponding to each error response output by the error response output unit and for obtaining, as operation information, a condition defining the operation of the calculating device upon receiving each error response, and an operation setting unit for setting operation condition at the time of a failure based on the operation information.Type: ApplicationFiled: February 4, 2011Publication date: August 11, 2011Applicant: FUJITSU LIMITEDInventors: Yusuke KURASAWA, Toshiaki Takeuchi, Masakazu Sakamoto, Tetsuya Kinoshita, Jun Takeuchi, Atsushi Shinohara
-
Publication number: 20110191519Abstract: A queue number acquiring unit acquires a command queuing number that is the upper limit of the number of process-waiting instructions that can be stored in each of storages that make up a virtual disk for each storage. A minimum queue number selecting unit selects the minimum value of the command queuing numbers of the storages that make up the virtual disk as a minimum queue number. A queue number setting unit sets the selected minimum queue number as the command queuing number of the virtual disk that includes the storage device of which the command queuing number is selected as the minimum queue number for each virtual disk.Type: ApplicationFiled: January 26, 2011Publication date: August 4, 2011Applicant: FUJITSU LIMITEDInventors: Toshiaki TAKEUCHI, Masakazu Sakamoto, Tetsuya Kinoshita, Jun Takeuchi, Atsushi Shinohara, Yusuke Kurasawa
-
Patent number: 7889639Abstract: The fiber channel switch is capable of protecting data even if communication for adjusting reserves of access rights, which is performed by communication means, is interrupted. The fiber channel switch comprises: a plurality of connection terminals connected to a host computer and a physical storage unit via fiber channels; a storage virtualization unit producing a virtual storage unit; a first communication unit for communicating with another fiber channel switch; an access adjusting unit for adjusting an access reserve between the fiber channel switches; a unit for setting a master-slave relation between the fiber channel switches; a block control unit for blocking access between the host computer and the physical storage unit via the fiber channel switch if the fiber channel switch is set as a slave when the communication between the fiber channel switches is interrupted.Type: GrantFiled: March 23, 2006Date of Patent: February 15, 2011Assignee: Fujitsu LimitedInventors: Jun Takeuchi, Toshitaka Yanagisawa, Tetsuya Kinoshita, Takashi Murayama, Toshiaki Takeuchi, Atsushi Shinohara, Yusuke Kurasawa