Patents by Inventor Yusuke Maeyama

Yusuke Maeyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200357882
    Abstract: A semiconductor device includes: a drift layer of a first conductivity type which is made of silicon carbide; a junction region formed on one main surface of the drift layer; a junction termination extended region of the drift layer, the junction termination extended region being formed outside the junction region when the one main surface is viewed in plan view, and the junction termination extended region containing an impurity of a second conductivity type opposite to the first conductivity type; and a guard ring region of the drift layer, the guard ring region being formed at a position overlapping the junction termination extended region when the one main surface is viewed in plan view, and the guard ring region containing the impurity of the second conductivity type with a concentration that is higher than that of the junction termination extended region, wherein in the junction termination extended region, the concentration of the impurity of the second conductivity type in a depth direction from the o
    Type: Application
    Filed: February 13, 2018
    Publication date: November 12, 2020
    Inventors: Akihiko SHIBUKAWA, Yusuke MAEYAMA, Shunichi NAKAMURA
  • Patent number: 9960228
    Abstract: A wide gap semiconductor device comprises a first conductive-type semiconductor layer (32); a second conductive-type region (41), (42) that is provided on the first conductive-type semiconductor layer (32); a first electrode (1), of which a part is disposed on the second conductive-type region (41), (42) and the other part is disposed on the first conductive-type semiconductor layer (32); an insulating layer (51), (52), (53) that is provided adjacent to the first electrode (10) on the first conductive-type semiconductor layer (32) and that extends to an end part of the wide gap semiconductor device; and a second electrode (20) that is provided between the first electrode (10) and the end part of the wide gap semiconductor device and that forms a schottky junction with the first conductive-type semiconductor layer (32).
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: May 1, 2018
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Yusuke Maeyama, Shunichi Nakamura, Atsushi Ogasawara, Ryohei Osawa, Akihiko Shibukawa
  • Publication number: 20170263697
    Abstract: A wide gap semiconductor device comprises a first conductive-type semiconductor layer (32); a second conductive-type region (41), (42) that is provided on the first conductive-type semiconductor layer (32); a first electrode (1), of which a part is disposed on the second conductive-type region (41), (42) and the other part is disposed on the first conductive-type semiconductor layer (32); an insulating layer (51), (52), (53) that is provided adjacent to the first electrode (10) on the first conductive-type semiconductor layer (32) and that extends to an end part of the wide gap semiconductor device; and a second electrode (20) that is provided between the first electrode (10) and the end part of the wide gap semiconductor device and that forms a schottky junction with the first conductive-type semiconductor layer (32).
    Type: Application
    Filed: August 27, 2015
    Publication date: September 14, 2017
    Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Yusuke MAEYAMA, Shunichi NAKAMURA, Atsushi OGASAWARA, Ryohei OSAWA, Akihiko SHIBUKAWA
  • Patent number: 9496366
    Abstract: A method for manufacturing a semiconductor device includes forming a thermal oxide film on one surface of an SiC substrate by thermal oxidation at a temperature of 1150° C. or above in a gas atmosphere including nitrogen and oxygen, and introducing highly-concentrated nitrogen to one surface of the SiC substrate while forming the thermal oxide film; forming a highly-concentrated n-type SiC layer on one surface of the SiC substrate such that the thermal oxide film is removed from one surface of the SiC substrate by etching and, thereafter, one surface of the SiC substrate is exposed to radicals so that Si—N bonded bodies and C—N bonded bodies on one surface of the SiC substrate are removed while leaving nitrogen introduced into a lattice of SiC out of highly-concentrated nitrogen introduced into one surface of the SiC substrate; and forming an ohmic electrode layer on one surface of the SiC substrate.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: November 15, 2016
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Yusuke Maeyama, Yoshiyuki Watanabe, Shunichi Nakamura
  • Publication number: 20160056260
    Abstract: A method for manufacturing a semiconductor device includes forming a thermal oxide film on one surface of an SiC substrate by thermal oxidation at a temperature of 1150° C. or above in a gas atmosphere including nitrogen and oxygen, and introducing highly-concentrated nitrogen to one surface of the SiC substrate while forming the thermal oxide film; forming a highly-concentrated n-type SiC layer on one surface of the SiC substrate such that the thermal oxide film is removed from one surface of the SiC substrate by etching and, thereafter, one surface of the SiC substrate is exposed to radicals so that Si—N bonded bodies and C—N bonded bodies on one surface of the SiC substrate are removed while leaving nitrogen introduced into a lattice of SiC out of highly-concentrated nitrogen introduced into one surface of the SiC substrate; and forming an ohmic electrode layer on one surface of the SiC substrate.
    Type: Application
    Filed: October 8, 2013
    Publication date: February 25, 2016
    Inventors: Yusuke MAEYAMA, Yoshiyuki WATANABE, Shunichi NAKAMURA
  • Patent number: 8937319
    Abstract: A third insulating layer is formed in a periphery region of a substrate over a first surface (main surface) of the substrate so as to straddle a second semiconductor layer closest to a guard ring layer and a second semiconductor layer closest to the second semiconductor layer. In other words, the third insulating layer is formed to cover a portion of the first semiconductor layer, which is exposed to the first surface (main surface) of the substrate and which is between the second semiconductor layers. Thereby, the third insulating layer electrically insulates the metal layer from the portion of the first semiconductor layer, which is exposed to the first surface (main surface) of the substrate and which is between the second semiconductor layers.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: January 20, 2015
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Yusuke Maeyama, Ryohei Osawa, Yoshitaka Araki, Yoshiyuki Watanabe
  • Publication number: 20120228636
    Abstract: A third insulating layer is formed in a periphery region of a substrate over a first surface (main surface) of the substrate so as to straddle a second semiconductor layer closest to a guard ring layer and a second semiconductor layer closest to the second semiconductor layer. In other words, the third insulating layer is formed to cover a portion of the first semiconductor layer, which is exposed to the first surface (main surface) of the substrate and which is between the second semiconductor layers. Thereby, the third insulating layer electrically insulates the metal layer from the portion of the first semiconductor layer, which is exposed to the first surface (main surface) of the substrate and which is between the second semiconductor layers.
    Type: Application
    Filed: March 2, 2012
    Publication date: September 13, 2012
    Inventors: Yusuke MAEYAMA, Ryohei Osawa, Yoshitaka Araki, Yoshiyuki Watanabe
  • Publication number: 20110169015
    Abstract: Disclosed is a bipolar semiconductor device which is capable of reducing the surface state density of a bipolar transistor and increasing the current gain of the transistor, thereby improving the transistor performance. A bipolar semiconductor device (100) has a surface protective film (30) on the surface of a semiconductor element. The surface protective film is composed of a thermal oxide film (31) formed on the surface of the semiconductor element, and a deposited oxide film (32) formed on the thermal oxide film. The deposited oxide film contains at least one of hydrogen element and nitrogen element in an amount of not less than 1018 cm?3.
    Type: Application
    Filed: August 25, 2009
    Publication date: July 14, 2011
    Applicants: HONDA MOTOR CO., LTD., SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Yuki Negoro, Akihiko Horiuchi, Kensuke Iwanaga, Seiichi Yokoyama, Hideki Hashimoto, Kenichi Nonaka, Yusuke Maeyama, Masashi Sato, Masaaki Shimizu
  • Patent number: 7544552
    Abstract: A method for manufacturing a junction semiconductor device, having a step for forming a first high-resistance layer, a step for forming a channel-doped layer, a step for forming a second high-resistance layer, a step for forming a low-resistance layer of a first conductive type that acts as a source region, a step for performing partial etching to a midway depth of the second high-resistance layer and the low-resistance layer, a step for forming a gate region below the portion etched in the etching step, and a step for forming a protective film on the surface of the region between the gate region and the source region. A gate region is formed using relatively low energy ion implantation in the surface that has been etched in advance to a height that is between the lower surface of the source area and the upper surface of the channel-doped layer.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: June 9, 2009
    Assignees: Honda Motor Co., Ltd., Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Ken-ichi Nonaka, Hideki Hashimoto, Seiichi Yokoyama, Kensuke Iwanaga, Yoshimitsu Saito, Hiroaki Iwakuro, Masaaki Shimizu, Yusuke Fukuda, Koichi Nishikawa, Yusuke Maeyama
  • Publication number: 20060214268
    Abstract: A semiconductor device includes: a passivation film; a first semiconductor layer that has a first main component of 4H—SiC of a first conductivity type; and a second semiconductor layer that has a second main component of 4H—SiC of a second conductivity type. The second semiconductor layer has a pn-junction with the first semiconductor layer. The pn-junction has a junction edge. The first and second semiconductor layers further include a local area that includes the junction edge. The local area has a first principal plane that interfaces with the passivation film. A normal to the first principal plane tilts by a first tilt angle in a range of 25 degrees to 45 degrees from a first axis of [0001] or [000-1] toward a second axis of <01-10>.
    Type: Application
    Filed: March 22, 2006
    Publication date: September 28, 2006
    Inventors: Yusuke Maeyama, Koichi Nishikawa, Yusuke Fukuda, Masaaki Shimizu, Masashi Satoh, Hiroaki Iwakuro, Kenichi Nonaka
  • Publication number: 20060216879
    Abstract: A method for manufacturing a junction semiconductor device, having a step for forming a first high-resistance layer, a step for forming a channel-doped layer, a step for forming a second high-resistance layer, a step for forming a low-resistance layer of a first conductive type that acts as a source region, a step for performing partial etching to a midway depth of the second high-resistance layer and the low-resistance layer, a step for forming a gate region below the portion etched in the etching step, and a step for forming a protective film on the surface of the region between the gate region and the source region. A gate region is formed using relatively low energy ion implantation in the surface that has been etched in advance to a height that is between the lower surface of the source area and the upper surface of the channel-doped layer.
    Type: Application
    Filed: March 23, 2006
    Publication date: September 28, 2006
    Inventors: Ken-ichi Nonaka, Hideki Hashimoto, Seiichi Yokoyama, Kensuke Iwanaga, Yoshimitsu Saito, Hiroaki Iwakuro, Masaaki Shimizu, Yusuke Fukuda, Koichi Nishikawa, Yusuke Maeyama